From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C234C433EF for ; Thu, 31 Mar 2022 16:31:18 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id ECEFD841AD; Thu, 31 Mar 2022 18:31:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="oSvZ4cfg"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EBE0483923; Thu, 31 Mar 2022 18:31:08 +0200 (CEST) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 17918841AD for ; Thu, 31 Mar 2022 18:30:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=p.yadav@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 22VGUs0N007258; Thu, 31 Mar 2022 11:30:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1648744254; bh=goDRZ2AbQYh6Tgnaf2rjT43PQwzjnBj5QLXFwFhHs2o=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=oSvZ4cfgU1Z1q6xsub5Q2Lat3FupRDC2LBF89OKTsu+Uxn9y5w9L2U0oyPaoIirOI 6DC8DFnfAZS8Uz/1dE4+gD/uKv27LxmbhPuITHyu68+V8PrPH3MkJuCnjeWxx14ufy DSB3GJfPFfmRPR7cXuuiz4vGIqttwKR+FxFoSKUk= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 22VGUs8O104214 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 31 Mar 2022 11:30:54 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 31 Mar 2022 11:30:53 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 31 Mar 2022 11:30:53 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 22VGUrGv013883; Thu, 31 Mar 2022 11:30:53 -0500 Date: Thu, 31 Mar 2022 22:00:52 +0530 From: Pratyush Yadav To: Tom Rini CC: , Jagan Teki , Vignesh Raghavendra Subject: Re: [PATCH 13/25] spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig Message-ID: <20220331163052.av45lnxwutel3ngi@ti.com> References: <20220330220735.908616-1-trini@konsulko.com> <20220330220735.908616-13-trini@konsulko.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20220330220735.908616-13-trini@konsulko.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean +Vignesh Hi Tom, On 30/03/22 06:07PM, Tom Rini wrote: > This is a little tricky since SoCFPGA has code to determine this as > runtime. Introduce a guard variable for platforms to select if they > have a static value to use. Then for ARCH_SOCFPGA, call > cm_get_qspi_controller_clk_hz() and otherwise continue the previous > behavior. > > Cc: Jagan Teki > Signed-off-by: Tom Rini > --- > arch/arm/mach-socfpga/misc_soc64.c | 1 + > configs/j7200_evm_a72_defconfig | 2 ++ > configs/j7200_evm_r5_defconfig | 2 ++ > configs/j721e_evm_a72_defconfig | 2 ++ > configs/j721e_evm_r5_defconfig | 2 ++ > configs/j721e_hs_evm_a72_defconfig | 2 ++ > configs/j721e_hs_evm_r5_defconfig | 2 ++ > configs/j721s2_evm_a72_defconfig | 2 ++ > configs/j721s2_evm_r5_defconfig | 2 ++ > configs/k2g_evm_defconfig | 2 ++ > configs/k2g_hs_evm_defconfig | 2 ++ > configs/stv0991_defconfig | 2 ++ > drivers/spi/Kconfig | 8 ++++++++ > drivers/spi/cadence_qspi.c | 4 +++- > drivers/spi/cadence_qspi.h | 1 + > include/configs/j721e_evm.h | 1 - > include/configs/j721s2_evm.h | 1 - > include/configs/k2g_evm.h | 4 ---- > include/configs/socfpga_common.h | 9 --------- > include/configs/socfpga_soc64_common.h | 5 ----- > include/configs/stv0991.h | 8 -------- > 21 files changed, 35 insertions(+), 29 deletions(-) > > diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c > index 7b973a79e807..2acdfad07b35 100644 > --- a/arch/arm/mach-socfpga/misc_soc64.c > +++ b/arch/arm/mach-socfpga/misc_soc64.c > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > > DECLARE_GLOBAL_DATA_PTR; > > diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig > index eb1d7d46b82a..3d0d1977ff99 100644 > --- a/configs/j7200_evm_a72_defconfig > +++ b/configs/j7200_evm_a72_defconfig > @@ -173,6 +173,8 @@ CONFIG_SOC_TI=y > CONFIG_SPI=y > CONFIG_DM_SPI=y > CONFIG_CADENCE_QSPI=y > +CONFIG_HAS_CQSPI_REF_CLK=y > +CONFIG_CQSPI_REF_CLK=133333333 > CONFIG_SYSRESET=y > CONFIG_SPL_SYSRESET=y > CONFIG_SYSRESET_TI_SCI=y > diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig > index e500a27bb692..0f4b006b80b5 100644 > --- a/configs/j7200_evm_r5_defconfig > +++ b/configs/j7200_evm_r5_defconfig > @@ -134,6 +134,8 @@ CONFIG_SOC_TI=y > CONFIG_SPI=y > CONFIG_DM_SPI=y > CONFIG_CADENCE_QSPI=y > +CONFIG_HAS_CQSPI_REF_CLK=y > +CONFIG_CQSPI_REF_CLK=133333333 This clock is configured to 166 MHz via device tree. I would prefer TI platforms to use device tree and not set CONFIG_HAS_CQSPI_REF_CLK at all. The clock _is_ 133 MHz by default but I think it is better if we just return an error when clk_get fails. > CONFIG_SYSRESET=y > CONFIG_SPL_SYSRESET=y > CONFIG_SYSRESET_TI_SCI=y [...] > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c > index db680618ee9b..7209bb43a776 100644 > --- a/drivers/spi/cadence_qspi.c > +++ b/drivers/spi/cadence_qspi.c > @@ -188,8 +188,10 @@ static int cadence_spi_probe(struct udevice *bus) > if (plat->ref_clk_hz == 0) { > ret = clk_get_by_index(bus, 0, &clk); > if (ret) { > -#ifdef CONFIG_CQSPI_REF_CLK > +#ifdef CONFIG_HAS_CQSPI_REF_CLK > plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK; > +#elif defined(CONFIG_ARCH_SOCFPGA) > + plat->ref_clk_hz = cm_get_qspi_controller_clk_hz(); While you are here, please change all this to use if (IS_ENABLED()) instead. > #else > return ret; > #endif [...] -- Regards, Pratyush Yadav Texas Instruments Inc.