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[2603:6081:7b01:cbda:2ef0:5dff:fedb:a8ba]) by smtp.gmail.com with ESMTPSA id 193-20020a3706ca000000b0067d3e4b5667sm12943374qkg.67.2022.03.31.10.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 10:41:28 -0700 (PDT) Date: Thu, 31 Mar 2022 13:41:26 -0400 From: Tom Rini To: Pratyush Yadav Cc: u-boot@lists.denx.de, Jagan Teki , Vignesh Raghavendra Subject: Re: [PATCH 13/25] spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig Message-ID: <20220331174126.GF14476@bill-the-cat> References: <20220330220735.908616-1-trini@konsulko.com> <20220330220735.908616-13-trini@konsulko.com> <20220331163052.av45lnxwutel3ngi@ti.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="BEfR2jmXRHrz4elx" Content-Disposition: inline In-Reply-To: <20220331163052.av45lnxwutel3ngi@ti.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean --BEfR2jmXRHrz4elx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 31, 2022 at 10:00:52PM +0530, Pratyush Yadav wrote: > +Vignesh >=20 > Hi Tom, >=20 > On 30/03/22 06:07PM, Tom Rini wrote: > > This is a little tricky since SoCFPGA has code to determine this as > > runtime. Introduce a guard variable for platforms to select if they > > have a static value to use. Then for ARCH_SOCFPGA, call > > cm_get_qspi_controller_clk_hz() and otherwise continue the previous > > behavior. > >=20 > > Cc: Jagan Teki > > Signed-off-by: Tom Rini > > --- > > arch/arm/mach-socfpga/misc_soc64.c | 1 + > > configs/j7200_evm_a72_defconfig | 2 ++ > > configs/j7200_evm_r5_defconfig | 2 ++ > > configs/j721e_evm_a72_defconfig | 2 ++ > > configs/j721e_evm_r5_defconfig | 2 ++ > > configs/j721e_hs_evm_a72_defconfig | 2 ++ > > configs/j721e_hs_evm_r5_defconfig | 2 ++ > > configs/j721s2_evm_a72_defconfig | 2 ++ > > configs/j721s2_evm_r5_defconfig | 2 ++ > > configs/k2g_evm_defconfig | 2 ++ > > configs/k2g_hs_evm_defconfig | 2 ++ > > configs/stv0991_defconfig | 2 ++ > > drivers/spi/Kconfig | 8 ++++++++ > > drivers/spi/cadence_qspi.c | 4 +++- > > drivers/spi/cadence_qspi.h | 1 + > > include/configs/j721e_evm.h | 1 - > > include/configs/j721s2_evm.h | 1 - > > include/configs/k2g_evm.h | 4 ---- > > include/configs/socfpga_common.h | 9 --------- > > include/configs/socfpga_soc64_common.h | 5 ----- > > include/configs/stv0991.h | 8 -------- > > 21 files changed, 35 insertions(+), 29 deletions(-) > >=20 > > diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga= /misc_soc64.c > > index 7b973a79e807..2acdfad07b35 100644 > > --- a/arch/arm/mach-socfpga/misc_soc64.c > > +++ b/arch/arm/mach-socfpga/misc_soc64.c > > @@ -16,6 +16,7 @@ > > #include > > #include > > #include > > +#include > > =20 > > DECLARE_GLOBAL_DATA_PTR; > > =20 > > diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_de= fconfig > > index eb1d7d46b82a..3d0d1977ff99 100644 > > --- a/configs/j7200_evm_a72_defconfig > > +++ b/configs/j7200_evm_a72_defconfig > > @@ -173,6 +173,8 @@ CONFIG_SOC_TI=3Dy > > CONFIG_SPI=3Dy > > CONFIG_DM_SPI=3Dy > > CONFIG_CADENCE_QSPI=3Dy > > +CONFIG_HAS_CQSPI_REF_CLK=3Dy > > +CONFIG_CQSPI_REF_CLK=3D133333333 > > CONFIG_SYSRESET=3Dy > > CONFIG_SPL_SYSRESET=3Dy > > CONFIG_SYSRESET_TI_SCI=3Dy > > diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defc= onfig > > index e500a27bb692..0f4b006b80b5 100644 > > --- a/configs/j7200_evm_r5_defconfig > > +++ b/configs/j7200_evm_r5_defconfig > > @@ -134,6 +134,8 @@ CONFIG_SOC_TI=3Dy > > CONFIG_SPI=3Dy > > CONFIG_DM_SPI=3Dy > > CONFIG_CADENCE_QSPI=3Dy > > +CONFIG_HAS_CQSPI_REF_CLK=3Dy > > +CONFIG_CQSPI_REF_CLK=3D133333333 >=20 > This clock is configured to 166 MHz via device tree. I would prefer TI=20 > platforms to use device tree and not set CONFIG_HAS_CQSPI_REF_CLK at=20 > all. The clock _is_ 133 MHz by default but I think it is better if we=20 > just return an error when clk_get fails. For these migration patches, it's important to not include functional changes as the same time in case there's problems later on (see for example the SYS_IMMR fix I merged today). So please send a follow-up to this patch or something vs master to disable the current behavior on the TI platforms. > > CONFIG_SYSRESET=3Dy > > CONFIG_SPL_SYSRESET=3Dy > > CONFIG_SYSRESET_TI_SCI=3Dy > [...] > > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c > > index db680618ee9b..7209bb43a776 100644 > > --- a/drivers/spi/cadence_qspi.c > > +++ b/drivers/spi/cadence_qspi.c > > @@ -188,8 +188,10 @@ static int cadence_spi_probe(struct udevice *bus) > > if (plat->ref_clk_hz =3D=3D 0) { > > ret =3D clk_get_by_index(bus, 0, &clk); > > if (ret) { > > -#ifdef CONFIG_CQSPI_REF_CLK > > +#ifdef CONFIG_HAS_CQSPI_REF_CLK > > plat->ref_clk_hz =3D CONFIG_CQSPI_REF_CLK; > > +#elif defined(CONFIG_ARCH_SOCFPGA) > > + plat->ref_clk_hz =3D cm_get_qspi_controller_clk_hz(); >=20 > While you are here, please change all this to use if (IS_ENABLED())=20 > instead. In this case IS_ENABLED() does not increase readibity of the code nor increase static code coverage testing. --=20 Tom --BEfR2jmXRHrz4elx Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmJF57wACgkQFHw5/5Y0 tywIZQv8CEQfhqcNCkBCDgp3c+l/mCLVtNTi9WFlDN55rdPrYorTGuH5ZVdquWZL 2h/2An8zEmw2W17AuV1bBeejtDaZGLzL2zrjiloBqKoU815Fe2mGziPVcObmG7Tl /lebqcuDH4muP8tsrdjo5A5caxbpiOhbs95FulyEQUaXt0EakHdYINWouPuMyMg7 CLh9JfVyadiLVYWtpwiD+ukS/BCzDgdHiU78itqat8I+bwni8uZklR8IiX5ujv98 oPRHgkcN2rgvEISC/w3kuNKfTzFNHwu8ILSNsgu/q9ACZnRJujRsBXmH2oFgOZEg xRGnjdw+0KLv6DUQVsaH01EtdrA1pThHy7XtypRUOFITV61+krC+5LH8PwsESnbs Rld//4LmGk42cFdudNbQF7rE3iAkY6Qjtm3mgQ5r2TcGOvbdX/qvQogCiXzOxEWO 5+me5bwaqOCFmT7seI5m6Mnv2yq8TlbbkeEJEb9RNqXTkkTmUcj78+hlgyXkEE+S 9yhnYx/a =W8GR -----END PGP SIGNATURE----- --BEfR2jmXRHrz4elx--