From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E422AC433F5 for ; Thu, 31 Mar 2022 23:30:45 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9745D842D8; Fri, 1 Apr 2022 01:24:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2E309842BE; Fri, 1 Apr 2022 01:23:18 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 04D4E842B5 for ; Fri, 1 Apr 2022 01:22:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7861E139F; Thu, 31 Mar 2022 16:22:52 -0700 (PDT) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 347533F73B; Thu, 31 Mar 2022 16:22:51 -0700 (PDT) Date: Fri, 1 Apr 2022 00:18:30 +0100 From: Andre Przywara To: Samuel Holland Cc: u-boot@lists.denx.de, Jagan Teki , Sean Anderson , Simon Glass , Heinrich Schuchardt , Heiko Schocher , Joe Hershberger Subject: Re: [PATCH v2 05/23] pinctrl: sunxi: Add UART pinmuxes Message-ID: <20220401001830.2b60bb29@slackpad.lan> In-Reply-To: <20220318035420.15058-6-samuel@sholland.org> References: <20220318035420.15058-1-samuel@sholland.org> <20220318035420.15058-6-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Thu, 17 Mar 2022 22:54:02 -0500 Samuel Holland wrote: > This includes UART0 and R_UART (s_uart) on all supported platforms, plus > the additional UART configurations from arch/arm/mach-sunxi/board.c. > > Pin lists and mux values were taken from the Linux drivers. > > Signed-off-by: Samuel Holland Compare against the individual manuals. Reviewed-by: Andre Przywara Cheers, Andre > --- > > (no changes since v1) > > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 98 +++++++++++++++++++++++++++ > 1 file changed, 98 insertions(+) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > index 24b9647054..751b47d687 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -225,6 +225,11 @@ static int sunxi_pinctrl_probe(struct udevice *dev) > static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 5 }, /* PE0-PE1 */ > +#endif > }; > > static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = { > @@ -237,6 +242,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc > static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 4 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PB22-PB23 */ > +#endif > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = { > @@ -249,6 +259,12 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 4 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PB19-PB20 */ > +#endif > + { "uart1", 4 }, /* PG3-PG4 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = { > @@ -261,6 +277,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PH20-PH21 */ > +#endif > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = { > @@ -273,6 +294,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > + { "s_uart", 2 }, /* PL2-PL3 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc = { > @@ -285,6 +307,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc = > static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 4 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PB22-PB23 */ > +#endif > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = { > @@ -297,6 +324,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#endif > + { "uart1", 2 }, /* PG6-PG7 */ > + { "uart2", 2 }, /* PB0-PB1 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = { > @@ -309,6 +341,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > + { "s_uart", 2 }, /* PL2-PL3 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc = { > @@ -321,6 +354,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc = > static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 3 }, /* PB0-PB1 */ > +#endif > + { "uart1", 2 }, /* PG6-PG7 */ > + { "uart2", 2 }, /* PB0-PB1 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = { > @@ -333,6 +373,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PB9-PB10 */ > +#endif > + { "uart1", 2 }, /* PG6-PG7 */ > + { "uart2", 2 }, /* PB0-PB1 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc = { > @@ -345,6 +392,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc = > static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > + { "s_uart", 2 }, /* PL2-PL3 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc = { > @@ -357,6 +405,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc > static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PA4-PA5 */ > +#endif > + { "uart1", 2 }, /* PG6-PG7 */ > + { "uart2", 2 }, /* PA0-PA1 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = { > @@ -369,6 +424,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > + { "s_uart", 2 }, /* PL2-PL3 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc = { > @@ -381,6 +437,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc = > static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 3 }, /* PB8-PB9 */ > +#endif > + { "uart1", 2 }, /* PG6-PG7 */ > + { "uart2", 2 }, /* PB0-PB1 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = { > @@ -393,6 +456,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 4 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PH12-PH13 */ > +#endif > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = { > @@ -405,6 +473,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > + { "s_uart", 3 }, /* PL0-PL1 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = { > @@ -417,6 +486,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = > static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 4 }, /* PB8-PB9 */ > +#endif > + { "uart1", 2 }, /* PG6-PG7 */ > + { "uart2", 2 }, /* PB0-PB1 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc = { > @@ -429,6 +505,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc = > static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > + { "s_uart", 2 }, /* PL2-PL3 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc = { > @@ -441,6 +518,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc > static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PA4-PA5 */ > +#endif > + { "uart1", 2 }, /* PG6-PG7 */ > + { "uart2", 2 }, /* PA0-PA1 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = { > @@ -453,6 +537,12 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PH0-PH1 */ > +#endif > + { "uart1", 2 }, /* PG6-PG7 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = { > @@ -465,6 +555,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = { > static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > + { "s_uart", 2 }, /* PL2-PL3 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc = { > @@ -477,6 +568,12 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc = > static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2-PF4 */ > +#else > + { "uart0", 2 }, /* PH0-PH1 */ > +#endif > + { "uart1", 2 }, /* PG6-PG7 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = { > @@ -489,6 +586,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = > static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > + { "s_uart", 2 }, /* PL2-PL3 */ > }; > > static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc = {