From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CF35C433EF for ; Thu, 31 Mar 2022 23:31:48 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 67B7484284; Fri, 1 Apr 2022 01:24:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4B425842D7; Fri, 1 Apr 2022 01:23:25 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 9A2C3842B6 for ; Fri, 1 Apr 2022 01:22:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E4029139F; Thu, 31 Mar 2022 16:22:54 -0700 (PDT) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BF7D43F73B; Thu, 31 Mar 2022 16:22:53 -0700 (PDT) Date: Fri, 1 Apr 2022 00:19:36 +0100 From: Andre Przywara To: Samuel Holland Cc: u-boot@lists.denx.de, Jagan Teki , Sean Anderson , Simon Glass , Heinrich Schuchardt , Heiko Schocher , Joe Hershberger Subject: Re: [PATCH v2 08/23] net: sunxi_emac: Remove non-DM pin setup Message-ID: <20220401001936.2a886b55@slackpad.lan> In-Reply-To: <20220318035420.15058-9-samuel@sholland.org> References: <20220318035420.15058-1-samuel@sholland.org> <20220318035420.15058-9-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Thu, 17 Mar 2022 22:54:05 -0500 Samuel Holland wrote: > This is now handled automatically by the pinctrl driver. > > Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Cheers, Andre > --- > > (no changes since v1) > > arch/arm/include/asm/arch-sunxi/gpio.h | 1 - > drivers/net/sunxi_emac.c | 7 +------ > 2 files changed, 1 insertion(+), 7 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h > index 773711b6a3..e93c9e84c9 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -135,7 +135,6 @@ enum sunxi_gpio_number { > #define SUNXI_GPIO_OUTPUT 1 > #define SUNXI_GPIO_DISABLE 7 > > -#define SUNXI_GPA_EMAC 2 > #define SUN6I_GPA_GMAC 2 > #define SUN7I_GPA_GMAC 5 > #define SUN8I_H3_GPA_UART0 2 > diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c > index 17ad88e732..d15b0add7c 100644 > --- a/drivers/net/sunxi_emac.c > +++ b/drivers/net/sunxi_emac.c > @@ -17,7 +17,6 @@ > #include > #include > #include > -#include > > /* EMAC register */ > struct emac_regs { > @@ -511,15 +510,11 @@ static int sunxi_emac_board_setup(struct udevice *dev, > struct sunxi_sramc_regs *sram = > (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; > struct emac_regs *regs = priv->regs; > - int pin, ret; > + int ret; > > /* Map SRAM to EMAC */ > setbits_le32(&sram->ctrl1, 0x5 << 2); > > - /* Configure pin mux settings for MII Ethernet */ > - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) > - sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC); > - > /* Set up clock gating */ > ret = clk_enable(&priv->clk); > if (ret) {