From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D388BC433F5 for ; Thu, 31 Mar 2022 23:28:36 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 05A71842D6; Fri, 1 Apr 2022 01:23:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4BC66842C1; Fri, 1 Apr 2022 01:23:05 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 8777D84272 for ; Fri, 1 Apr 2022 01:22:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3DF8913D5; Thu, 31 Mar 2022 16:22:42 -0700 (PDT) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EDACA3F73B; Thu, 31 Mar 2022 16:22:40 -0700 (PDT) Date: Fri, 1 Apr 2022 00:20:05 +0100 From: Andre Przywara To: Samuel Holland Cc: u-boot@lists.denx.de, Jagan Teki , Sean Anderson , Simon Glass , Heinrich Schuchardt , Heiko Schocher , Joe Hershberger Subject: Re: [PATCH v2 10/23] sunxi: Remove non-DM GMAC pin setup Message-ID: <20220401002005.0403d361@slackpad.lan> In-Reply-To: <20220318035420.15058-11-samuel@sholland.org> References: <20220318035420.15058-1-samuel@sholland.org> <20220318035420.15058-11-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Thu, 17 Mar 2022 22:54:07 -0500 Samuel Holland wrote: > This is now handled automatically by the pinctrl driver. > > Signed-off-by: Samuel Holland Yeah! Reviewed-by: Andre Przywara Cheers, Andre > --- > > (no changes since v1) > > arch/arm/include/asm/arch-sunxi/gpio.h | 2 - > board/sunxi/gmac.c | 55 -------------------------- > 2 files changed, 57 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h > index e93c9e84c9..2aa6bbb178 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -135,8 +135,6 @@ enum sunxi_gpio_number { > #define SUNXI_GPIO_OUTPUT 1 > #define SUNXI_GPIO_DISABLE 7 > > -#define SUN6I_GPA_GMAC 2 > -#define SUN7I_GPA_GMAC 5 > #define SUN8I_H3_GPA_UART0 2 > > #define SUN4I_GPB_PWM 2 > diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c > index 1fa54ed72d..2a885305eb 100644 > --- a/board/sunxi/gmac.c > +++ b/board/sunxi/gmac.c > @@ -1,13 +1,11 @@ > #include > #include > #include > -#include > #include > #include > > void eth_init_board(void) > { > - int pin; > struct sunxi_ccm_reg *const ccm = > (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; > > @@ -21,57 +19,4 @@ void eth_init_board(void) > setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | > CCM_GMAC_CTRL_GPIT_MII); > #endif > - > -#ifndef CONFIG_MACH_SUN6I > - /* Configure pin mux settings for GMAC */ > -#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR > - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) { > -#else > - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { > -#endif > -#ifdef CONFIG_RGMII > - /* skip unused pins in RGMII mode */ > - if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) > - continue; > -#endif > - sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC); > - sunxi_gpio_set_drv(pin, 3); > - } > -#elif defined CONFIG_RGMII > - /* Configure sun6i RGMII mode pin mux settings */ > - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > - sunxi_gpio_set_drv(pin, 3); > - } > - for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > - sunxi_gpio_set_drv(pin, 3); > - } > - for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) { > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > - sunxi_gpio_set_drv(pin, 3); > - } > - for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) { > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > - sunxi_gpio_set_drv(pin, 3); > - } > -#elif defined CONFIG_GMII > - /* Configure sun6i GMII mode pin mux settings */ > - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) { > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > - sunxi_gpio_set_drv(pin, 2); > - } > -#else > - /* Configure sun6i MII mode pin mux settings */ > - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > - for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++) > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > - for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++) > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > - for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++) > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > - for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) > - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); > -#endif > }