From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E38D2C433EF for ; Thu, 31 Mar 2022 23:26:41 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 61D06842B9; Fri, 1 Apr 2022 01:22:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D006E84289; Fri, 1 Apr 2022 01:22:44 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 6A32C8429B for ; Fri, 1 Apr 2022 01:22:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 88981139F; Thu, 31 Mar 2022 16:22:31 -0700 (PDT) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 42B1B3F73B; Thu, 31 Mar 2022 16:22:30 -0700 (PDT) Date: Fri, 1 Apr 2022 00:20:51 +0100 From: Andre Przywara To: Samuel Holland Cc: u-boot@lists.denx.de, Jagan Teki , Sean Anderson , Simon Glass , Heinrich Schuchardt , Heiko Schocher , Joe Hershberger Subject: Re: [PATCH v2 17/23] i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C Message-ID: <20220401002051.53792af3@slackpad.lan> In-Reply-To: <20220318035420.15058-18-samuel@sholland.org> References: <20220318035420.15058-1-samuel@sholland.org> <20220318035420.15058-18-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Thu, 17 Mar 2022 22:54:14 -0500 Samuel Holland wrote: > When the DM_I2C driver is loaded, the pin setup is done automatically > from the device tree by the pinctrl driver. > > Clean up the code in the process: remove #ifdefs and recognize that the > pin configuration is the same for all sun8i/sun50i SoCs, not just those > which select CONFIG_MACH_SUN8I. Indeed, even though the F1C100s uses mux 4, but we don't use the RSB there, and can fix that when we need it. So this means we could enable RSB for the H616 SPL? Regardless this looks alright: Reviewed-by: Andre Przywara Cheers, Andre > > Signed-off-by: Samuel Holland > --- > > (no changes since v1) > > drivers/i2c/sun8i_rsb.c | 46 +++++++++++++++++------------------------ > 1 file changed, 19 insertions(+), 27 deletions(-) > > diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c > index 716b245a00..0dea8f7a92 100644 > --- a/drivers/i2c/sun8i_rsb.c > +++ b/drivers/i2c/sun8i_rsb.c > @@ -95,27 +95,6 @@ static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base, > return sun8i_rsb_do_trans(base); > } > > -static void sun8i_rsb_cfg_io(void) > -{ > -#ifdef CONFIG_MACH_SUN8I > - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); > - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); > - sunxi_gpio_set_pull(SUNXI_GPL(0), 1); > - sunxi_gpio_set_pull(SUNXI_GPL(1), 1); > - sunxi_gpio_set_drv(SUNXI_GPL(0), 2); > - sunxi_gpio_set_drv(SUNXI_GPL(1), 2); > -#elif defined CONFIG_MACH_SUN9I > - sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB); > - sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB); > - sunxi_gpio_set_pull(SUNXI_GPN(0), 1); > - sunxi_gpio_set_pull(SUNXI_GPN(1), 1); > - sunxi_gpio_set_drv(SUNXI_GPN(0), 2); > - sunxi_gpio_set_drv(SUNXI_GPN(1), 2); > -#else > -#error unsupported MACH_SUNXI > -#endif > -} > - > static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base) > { > u32 div = 0; > @@ -147,12 +126,6 @@ static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base) > > static int sun8i_rsb_init(struct sunxi_rsb_reg *base) > { > - /* Enable RSB and PIO clk, and de-assert their resets */ > - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); > - > - /* Setup external pins */ > - sun8i_rsb_cfg_io(); > - > writel(RSB_CTRL_SOFT_RST, &base->ctrl); > sun8i_rsb_set_clk(base); > > @@ -185,6 +158,25 @@ int rsb_init(void) > { > struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; > > + /* Enable RSB and PIO clk, and de-assert their resets */ > + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); > + > + if (IS_ENABLED(CONFIG_MACH_SUN9I)) { > + sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB); > + sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB); > + sunxi_gpio_set_pull(SUNXI_GPN(0), 1); > + sunxi_gpio_set_pull(SUNXI_GPN(1), 1); > + sunxi_gpio_set_drv(SUNXI_GPN(0), 2); > + sunxi_gpio_set_drv(SUNXI_GPN(1), 2); > + } else { > + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); > + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); > + sunxi_gpio_set_pull(SUNXI_GPL(0), 1); > + sunxi_gpio_set_pull(SUNXI_GPL(1), 1); > + sunxi_gpio_set_drv(SUNXI_GPL(0), 2); > + sunxi_gpio_set_drv(SUNXI_GPL(1), 2); > + } > + > return sun8i_rsb_init(base); > } > #endif