From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 146DAC433F5 for ; Fri, 1 Apr 2022 11:42:17 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 14ADB80A4F; Fri, 1 Apr 2022 13:41:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="OdWtm398"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7ECF884230; Fri, 1 Apr 2022 11:30:10 +0200 (CEST) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5329A8428D for ; Fri, 1 Apr 2022 11:30:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Sergiu.Moga@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1648805400; x=1680341400; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ji6jfkQR7flIamOsjqOA+W3sWJvec4/FW7iXqZ2pBuI=; b=OdWtm398SRHZ98BynXyS+vVhHzbW4mtpacu7NhD1PyFuJ7ttZUL15vfN 3SvCoNEpysJMaJTP2tDCEh7UyGmcOHjyKdi7MKDp2P6vewft74tMPjhm9 lyBYVXxcRJf+lLXAT4XTH/YglOwJQmAiVA1oqFTQmVuKykSs2ZyAH/A/e 58TIK1v66Rx9hdKdnJvtcP2XbfHut6KXfVdoiCS9jCKmWnH2f3BjDrN/A ToyMpyQglmBblqBneROkeRjA6EGl8bf9CzACIlZZ6NImDFexxRm50Cimq +OJKDoKgZcZA11H4wBEuDhnabLxU2wZ0ef4BLaxPjKsyp+rr1AmJRw87d g==; X-IronPort-AV: E=Sophos;i="5.90,226,1643698800"; d="scan'208";a="167968539" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2022 02:29:58 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Apr 2022 02:29:57 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Apr 2022 02:29:51 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , CC: , Sergiu Moga Subject: [PATCH 2/5] sysreset: Add Atmel/Microchip sysreset driver Date: Fri, 1 Apr 2022 12:27:24 +0300 Message-ID: <20220401092727.9866-3-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220401092727.9866-1-sergiu.moga@microchip.com> References: <20220401092727.9866-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Mailman-Approved-At: Fri, 01 Apr 2022 13:41:38 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean This patch adds a sysreset driver for Atmel/Microchip platforms. Signed-off-by: Sergiu Moga Reviewed-by: Claudiu Beznea --- drivers/sysreset/Kconfig | 15 +++++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_at91.c | 71 ++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/sysreset/sysreset_at91.c diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index f6d60038b8..25dd02c704 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -77,6 +77,21 @@ config SYSRESET_OCTEON This enables the system reset driver support for Marvell Octeon SoCs. +config SYSRESET_AT91 + bool "Enable support for Microchip/Atmel reset driver" + depends on ARCH_AT91 + select SYSRESET_SPL_AT91 if SPL && SPL_SYSRESET + help + This enables the system reset driver support for Microchip/Atmel + SoCs. + +config SYSRESET_SPL_AT91 + bool "Enable support for Microchip/Atmel reset driver in SPL" + depends on ARCH_AT91 + help + This enables the system reset driver support for Microchip/Atmel + SoCs in SPL. + config SYSRESET_PSCI bool "Enable support for PSCI System Reset" depends on ARM_PSCI_FW diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 8e00be0779..0ed3bbf356 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -20,5 +20,6 @@ obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o +obj-$(CONFIG_SYSRESET_$(SPL_TPL_)AT91) += sysreset_at91.o obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c new file mode 100644 index 0000000000..24b87ee987 --- /dev/null +++ b/drivers/sysreset/sysreset_at91.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int at91_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + at91_rstc_t *rstc = (at91_rstc_t *)dev_get_priv(dev); + + writel(AT91_RSTC_KEY + | AT91_RSTC_CR_PROCRST /* Processor Reset */ + | AT91_RSTC_CR_PERRST /* Peripheral Reset */ +#ifdef CONFIG_AT91RESET_EXTRST + | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */ +#endif + , &rstc->cr); + + return -EINPROGRESS; +} + +static int at91_sysreset_probe(struct udevice *dev) +{ + struct clk slck; + void *priv; + int ret; + + priv = dev_remap_addr(dev); + if (!priv) + return -EINVAL; + + dev_set_priv(dev, priv); + + ret = clk_get_by_index(dev, 0, &slck); + if (ret) + return ret; + + ret = clk_prepare_enable(&slck); + if (ret) + return ret; + + return 0; +} + +static struct sysreset_ops at91_sysreset = { + .request = at91_sysreset_request, +}; + +static const struct udevice_id a91_sysreset_ids[] = { + { .compatible = "atmel,sama5d3-rstc" }, + { .compatible = "microchip,sam9x60-rstc" }, + { } +}; + +U_BOOT_DRIVER(sysreset_at91) = { + .id = UCLASS_SYSRESET, + .name = "at91_reset", + .ops = &at91_sysreset, + .probe = at91_sysreset_probe, + .of_match = a91_sysreset_ids, +}; -- 2.25.1