From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9822DC433F5 for ; Fri, 1 Apr 2022 13:45:09 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 20EF484310; Fri, 1 Apr 2022 15:42:46 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=semihalf.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=semihalf-com.20210112.gappssmtp.com header.i=@semihalf-com.20210112.gappssmtp.com header.b="0jb6PuCe"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6941B842A6; Fri, 1 Apr 2022 14:44:49 +0200 (CEST) Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B0FE0842EA for ; Fri, 1 Apr 2022 14:44:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=semihalf.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=pan@semihalf.com Received: by mail-wr1-x435.google.com with SMTP id w21so4130649wra.2 for ; Fri, 01 Apr 2022 05:44:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ouvBbDYbtoBXgj5epeh7PAgujz8k6gOvNSCV9B7eBY=; b=0jb6PuCe0YG8/YStatD0vmTI50rhYe0BQ3hmZ3bnR/JHeL2P4gL1qPGuEtQP+D6Rvu +w2/ae1dG4AeYHCo+kjo9YHO2xzwOaYGuw47fsdxE0YkGOk9xhzwubrMhkk8IXEpJqGJ mfg4ynaMAfE3EjiCMkvk+AbGUhRy32jvFOyvGfX0oqnrec4igwsI5AtSxN7q4JjhUboA sPDfS6VqQRtdWdWWv0OJAze/MsXUm/Q7U5ECT35Car36vVdVnlMBRYptFYPOXDoIy4Xs JDGt/yy/Yv5zg0Tha9OE1x4TVo5G0aBcQy71A2DGPqXz6shA8f3GKjW1xqUy41Y9tbTi Ysng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ouvBbDYbtoBXgj5epeh7PAgujz8k6gOvNSCV9B7eBY=; b=jynDZeQu/1unu91Oiczm0vwV67sfH4Jm9GxFVg0ePqLANtGeyt2aLauY7NdMqVFfRe LBAgIu6WwvcuLgKSrRn+/bm7NMHfqoexXx0/XvBxlNQkVaCktsWReQgBfFG/dvg78biM b2MAnJ1x6PvdqOW3TC54dAkYfA8tYnzDadVxH2mbr3urddLw9gZ9C1ZSB5egOU+KQy6M ePGnM17ypnKEf6qGj1fLf0/egdKQSZl2rVKtwiyImHHgdh9WfRB81Llp2O4c51x20UO6 UoyluRAReQwb1sDvRQLsBfWgDAQKqzUeRE98wkDiIfVD7OrdGdrGL28AeyZKHKA6H7BF Ik1Q== X-Gm-Message-State: AOAM533G0fitqmJXYQ7/7X3G2Z3IZXpfFoX6N/HuKzB2IxMMsVdLENoi xamzwA9QtdmeipW09Wa4VCYWSA== X-Google-Smtp-Source: ABdhPJyOebfRBujzYMqvViWPJKN8RLRpFGETax8sw5hgUaf1UWpiMnP3nJ83uXqy2clIV0cGmPM0pg== X-Received: by 2002:a5d:6405:0:b0:204:1ef:56e8 with SMTP id z5-20020a5d6405000000b0020401ef56e8mr7786258wru.677.1648817056500; Fri, 01 Apr 2022 05:44:16 -0700 (PDT) Received: from localhost.localdomain ([85.191.191.191]) by smtp.gmail.com with ESMTPSA id o10-20020a5d47ca000000b00203fb25165esm2478175wrc.6.2022.04.01.05.44.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Apr 2022 05:44:16 -0700 (PDT) From: =?UTF-8?q?Pawe=C5=82=20Anikiel?= To: marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com, michal.simek@xilinx.com Cc: u-boot@lists.denx.de, sjg@chromium.org, festevam@denx.de, jagan@amarulasolutions.com, andre.przywara@arm.com, narmstrong@baylibre.com, pbrobinson@gmail.com, tharvey@gateworks.com, paul.liu@linaro.org, christianshewitt@gmail.com, adrian.fiergolski@fastree3d.com, marek.behun@nic.cz, wd@denx.de, elly.siew.chin.lim@intel.com, mw@semihalf.com, =?UTF-8?q?Pawe=C5=82=20Anikiel?= Subject: [PATCH 11/11] socfpga: arria10: Allow dcache_enable before relocation Date: Fri, 1 Apr 2022 14:43:25 +0200 Message-Id: <20220401124325.1810108-12-pan@semihalf.com> X-Mailer: git-send-email 2.35.1.1094.g7c7d902a7c-goog In-Reply-To: <20220401124325.1810108-1-pan@semihalf.com> References: <20220401124325.1810108-1-pan@semihalf.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Fri, 01 Apr 2022 15:42:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Before relocating to SDRAM, the ECC is initialized by clearing the whole SDRAM. In order to speed this up, dcache_enable is used (see sdram_init_ecc_bits). Since commit 503eea451903 ("arm: cp15: update DACR value to activate access control"), this no longer works, because running code in OCRAM with the XN bit set causes a page fault. Override dram_bank_mmu_setup to disable XN in the OCRAM and setup DRAM dcache before relocation. Signed-off-by: Paweł Anikiel --- arch/arm/mach-socfpga/misc_arria10.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 0ed2adfd84..7ce888d197 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -246,3 +246,29 @@ int qspi_flash_software_reset(void) return 0; } #endif + +void dram_bank_mmu_setup(int bank) +{ + struct bd_info *bd = gd->bd; + u32 start, size; + int i; + + /* If we're still in OCRAM, don't set the XN bit on it */ + if (!(gd->flags & GD_FLG_RELOC)) { + set_section_dcache( + CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, + DCACHE_WRITETHROUGH); + } + + /* + * The default implementation of this function allows the DRAM dcache + * to be enabled only after relocation. However, to speed up ECC + * initialization, we want to be able to enable DRAM dcache before + * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram + * is set first). + */ + start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + for (i = start; i < start + size; i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +} -- 2.35.1.1094.g7c7d902a7c-goog