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Fri, 01 Apr 2022 05:44:06 -0700 (PDT) From: =?UTF-8?q?Pawe=C5=82=20Anikiel?= To: marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com, michal.simek@xilinx.com Cc: u-boot@lists.denx.de, sjg@chromium.org, festevam@denx.de, jagan@amarulasolutions.com, andre.przywara@arm.com, narmstrong@baylibre.com, pbrobinson@gmail.com, tharvey@gateworks.com, paul.liu@linaro.org, christianshewitt@gmail.com, adrian.fiergolski@fastree3d.com, marek.behun@nic.cz, wd@denx.de, elly.siew.chin.lim@intel.com, mw@semihalf.com, =?UTF-8?q?Pawe=C5=82=20Anikiel?= Subject: [PATCH 03/11] arm: dts: Add Chameleonv3 devicetree Date: Fri, 1 Apr 2022 14:43:17 +0200 Message-Id: <20220401124325.1810108-4-pan@semihalf.com> X-Mailer: git-send-email 2.35.1.1094.g7c7d902a7c-goog In-Reply-To: <20220401124325.1810108-1-pan@semihalf.com> References: <20220401124325.1810108-1-pan@semihalf.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Fri, 01 Apr 2022 15:42:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Add devicetree for Google Chameleon V3 board Signed-off-by: Paweł Anikiel --- arch/arm/dts/Makefile | 2 ++ arch/arm/dts/socfpga_chameleonv3.dtsi | 21 +++++++++++++++++++++ arch/arm/dts/socfpga_chameleonv3_270_3.dts | 9 +++++++++ arch/arm/dts/socfpga_chameleonv3_480_2.dts | 9 +++++++++ 4 files changed, 41 insertions(+) create mode 100644 arch/arm/dts/socfpga_chameleonv3.dtsi create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3.dts create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index beaaf15131..0ec4a4cab6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -411,6 +411,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_chameleonv3_270_3.dtb \ + socfpga_chameleonv3_480_2.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_is1.dtb \ socfpga_cyclone5_socdk.dtb \ diff --git a/arch/arm/dts/socfpga_chameleonv3.dtsi b/arch/arm/dts/socfpga_chameleonv3.dtsi new file mode 100644 index 0000000000..8b6a6cd8e4 --- /dev/null +++ b/arch/arm/dts/socfpga_chameleonv3.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_mercury_aa1.dtsi" + +&gmac0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_chameleonv3_270_3.dts b/arch/arm/dts/socfpga_chameleonv3_270_3.dts new file mode 100644 index 0000000000..2e29d052e3 --- /dev/null +++ b/arch/arm/dts/socfpga_chameleonv3_270_3.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; + +#include "socfpga_chameleonv3_270_3_handoff.h" +#include "socfpga_arria10-handoff.dtsi" +#include "socfpga_chameleonv3.dtsi" diff --git a/arch/arm/dts/socfpga_chameleonv3_480_2.dts b/arch/arm/dts/socfpga_chameleonv3_480_2.dts new file mode 100644 index 0000000000..3273f216f2 --- /dev/null +++ b/arch/arm/dts/socfpga_chameleonv3_480_2.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; + +#include "socfpga_chameleonv3_480_2_handoff.h" +#include "socfpga_arria10-handoff.dtsi" +#include "socfpga_chameleonv3.dtsi" -- 2.35.1.1094.g7c7d902a7c-goog