From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C0E8C433F5 for ; Fri, 1 Apr 2022 13:44:30 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D449F842F0; Fri, 1 Apr 2022 15:42:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=semihalf.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=semihalf-com.20210112.gappssmtp.com header.i=@semihalf-com.20210112.gappssmtp.com header.b="7U+T/VrR"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C3F22842C1; Fri, 1 Apr 2022 14:44:35 +0200 (CEST) Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 524B3842B7 for ; Fri, 1 Apr 2022 14:44:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=semihalf.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=pan@semihalf.com Received: by mail-wr1-x42b.google.com with SMTP id r13so4061617wrr.9 for ; Fri, 01 Apr 2022 05:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xZNgNFEG9PlZNEVmetKRc7qp5ztWRy8/zA3vwTZm8w8=; b=7U+T/VrRq7uKyypTqT3tPVP+2Wb7ejU4fB6O6ZA2MtPY1jJPq249j7R2V2a1mJydU4 g3VBy83deCf2wpa1F9xL633SqSt6xgM5QZEzItqzI6h0kK/gAa0Tuyh7dmCUBRTQSvPR dOUHHQYJ79EYsCo1EOCvCpVlaxlfyttRTUz1PxAjzch5HUMY/aJymc4DqLP1QiLs43By 3ufkffkV4oVtzr9EZd27Os2bV3pQqny7AyvIL/EAvGkVYmcd9Rxd8kvFZDCNNIhsrSve VUGKMs++IMc/b4hPICmqi6a2xUXij+Z1URDaJ3PncD7aTCllNGDclFh7khJJzwEFmlYf /B/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xZNgNFEG9PlZNEVmetKRc7qp5ztWRy8/zA3vwTZm8w8=; b=zZQqqOIT84F5OHOSMdzAjMtgnU7RvznJXvLa6vUSAXzjsNRTkk8OPU/cqmitzf//kB 8EwLtcmuta6g2x9ccffAf4C06w7nEc5tkzG8FhXxvq1hOILbU8JTjvgelJi1yXVZ1DBr cse4hUCA+zs26lfKtcqsPYU9hopijVZyUYnI5ZKjlGIonofmkYdBBLU/4ni42toE3chE c9H/6uLJ0MGfuDwcUS7tPsaIbo3KYhu/7IqlCmaktlydPO2Q51G1wEnt7Ll6AMYb70Oo GfZ2AaBbnD4vKRE2K/+GyKKoG0Z5WFI2FTcFcSsm3UTy6BNybFDeeH+vitZ743LrtGQ/ rzhQ== X-Gm-Message-State: AOAM530oVT0zYi4+zMS3VSqZqrCkQcqxE79qg6DWzGss8hyZRJrwwF/T UNg2l7aba8OOS0HfsmW/K8Hkqw== X-Google-Smtp-Source: ABdhPJw0BFScEje2XoogHi3fu/u6eJJmK5CDF0x9pJbuR7gTlnawIq8gZADTu3lgRJ65UXLBwK/Sng== X-Received: by 2002:a5d:640a:0:b0:204:619:4354 with SMTP id z10-20020a5d640a000000b0020406194354mr7587628wru.43.1648817052890; Fri, 01 Apr 2022 05:44:12 -0700 (PDT) Received: from localhost.localdomain ([85.191.191.191]) by smtp.gmail.com with ESMTPSA id o10-20020a5d47ca000000b00203fb25165esm2478175wrc.6.2022.04.01.05.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Apr 2022 05:44:12 -0700 (PDT) From: =?UTF-8?q?Pawe=C5=82=20Anikiel?= To: marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com, michal.simek@xilinx.com Cc: u-boot@lists.denx.de, sjg@chromium.org, festevam@denx.de, jagan@amarulasolutions.com, andre.przywara@arm.com, narmstrong@baylibre.com, pbrobinson@gmail.com, tharvey@gateworks.com, paul.liu@linaro.org, christianshewitt@gmail.com, adrian.fiergolski@fastree3d.com, marek.behun@nic.cz, wd@denx.de, elly.siew.chin.lim@intel.com, mw@semihalf.com, =?UTF-8?q?Pawe=C5=82=20Anikiel?= Subject: [PATCH 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg Date: Fri, 1 Apr 2022 14:43:22 +0200 Message-Id: <20220401124325.1810108-9-pan@semihalf.com> X-Mailer: git-send-email 2.35.1.1094.g7c7d902a7c-goog In-Reply-To: <20220401124325.1810108-1-pan@semihalf.com> References: <20220401124325.1810108-1-pan@semihalf.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Fri, 01 Apr 2022 15:42:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Using udelay while the clocks aren't fully configured causes the timer system to save the wrong clock rate. Use sdelay and wait_on_value instead (the values used in these functions were found experimentally). Signed-off-by: Paweł Anikiel --- arch/arm/mach-socfpga/clock_manager.c | 7 ++++--- arch/arm/mach-socfpga/clock_manager_arria10.c | 12 ++++++------ arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++ 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 9e645a4253..c9bd4859f7 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -39,9 +39,10 @@ void cm_wait_for_lock(u32 mask) /* function to poll in the fsm busy bit */ int cm_wait_for_fsm(void) { - return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() + - CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000, - false); + void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT); + + /* 20s timeout */ + return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 100000000); } int set_cpu_clk_info(void) diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 58d5d3fd8a..daa06b9d03 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -551,13 +551,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, CLKMGR_MAINPLL_VCO1_DENOM_LSB) | cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); - mdelay(1); + sdelay(1000000); /* 1ms */ cm_wait_for_lock(LOCKED_MASK); } writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | main_cfg->vco1_numer, socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); - mdelay(1); + sdelay(1000000); /* 1ms */ cm_wait_for_lock(LOCKED_MASK); } @@ -585,13 +585,13 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, clk_hz), socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); - mdelay(1); + sdelay(1000000); /* 1ms */ cm_wait_for_lock(LOCKED_MASK); } writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | per_cfg->vco1_numer, socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); - mdelay(1); + sdelay(1000000); /* 1ms */ cm_wait_for_lock(LOCKED_MASK); } @@ -727,7 +727,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); /* Wait for at least 5 us */ - udelay(5); + sdelay(5000); /* Now deassert BGPWRDN and PWRDN */ clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0, @@ -738,7 +738,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); /* Wait for at least 7 us */ - udelay(7); + sdelay(7000); /* enable the VCO and disable the external regulator to PLL */ writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) & diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index a8cb07a1c4..78013f0527 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -20,6 +20,10 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #endif #endif +void sdelay(unsigned long loops); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, + u32 bound); + #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -- 2.35.1.1094.g7c7d902a7c-goog