From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51B28C433EF for ; Fri, 1 Apr 2022 14:55:14 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 851FC83BF4; Fri, 1 Apr 2022 16:55:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1648824911; bh=Sd449+8AJ4oesJ7kZp27Y4bYErnmIPa1LKsVqKPnQIQ=; h=From:To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From; b=ZAfRkxX79sCdzLBkqMx1ErOyBYM+ApedOqNt2x+/KAdQibeBdkhWdMwuXYlVfb5TO 7GR5mEnTxzEDWk4BRyCDqFJIPAe+RXRf7y0mWmCF7Q+AG+4kiGlA1xtHDqbg4veFk6 +k6YX+03MuFH5XQIF3TKkrwIxGud7bqn5WwAf0meg9yQkUSYU82HCubOA9K8G7IVaI GxEtoQapUdd3y6NHfvBEvbfU/t8Gvdk8XfTvQTqpfJyp/lx44Dw3LHRLRS6Gt232px AJBF7SDTfEyY3d0ESe+v1kqT8PygNMx53y0mKDRWMOUpv9NEgEF6L/0xwJa4F2j3ir evG8qzgq8QSxA== Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id D8A4883B06; Fri, 1 Apr 2022 16:55:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1648824909; bh=Sd449+8AJ4oesJ7kZp27Y4bYErnmIPa1LKsVqKPnQIQ=; h=From:To:Cc:Subject:Date:From; b=g8H1GPEk7k4IumvgQFKaRnaV4Jn3zorPjznRA18qFbAO6aw/mIhErJulaDinCF060 /L7XJFeNykEJAtbeyjyOU+mJNJnnOAdqG3JIbeZH2sXGNGgm8C26Z0c69VPFPDr8OD ZaNvO9sClz8dfyG2KK8FgrBhFDvc00v009IBG70a+V2tanETSRiC17h1Tji631HHWx wsJQv1VpjTlQbGb4thLR/jaRWCuBcwxYUx+2rbjssNIaVglOVawbH5QeXDNG6LLxmX 1MouJBJT/QCK3Lpg6NYpG17dlPIn4UKS0JMsf/yrnboWsZukkC7f8Uz62LyeuYWSSb r/ViINIteMrog== From: Marek Vasut To: u-boot@lists.denx.de Cc: Marek Vasut , Fabio Estevam , Peng Fan , Stefano Babic Subject: [PATCH] arm: dts: imx8mp: Import GPCv2 subset, HSIOMIX and USB PD Date: Fri, 1 Apr 2022 16:54:48 +0200 Message-Id: <20220401145448.231134-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Add DT bindings for a subset of GPCv2 which handles USB and PCIe PDs, HSIOMIX PD controller and missing USB PD properties. This is required to bring up the DWC3 USB controller up. This is based on linux next and patches which are still pending review, but which are likely going to be part of Linux 5.19: b2d67d7bdf74 ("arm64: dts: imx8mp: disable usb3_phy1") 290918c72a29 ("arm64: dts: imx8mp: Add memory for USB3 glue layer to usb3 nodes") https://www.spinics.net/lists/arm-kernel/msg958501.html Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic --- arch/arm/dts/imx8mp.dtsi | 72 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index f9d64253c8a..79b65750da9 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -434,6 +435,44 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mp-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_pcie_phy: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_usb1_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_usb2_phy: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_hsiomix: power-domains@17 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_HSIO_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + }; + }; + }; }; aips2: bus@30400000 { @@ -842,6 +881,28 @@ }; }; + aips4: bus@32c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hsio_blk_ctrl: blk-ctrl@32f10000 { + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; + reg = <0x32f10000 0x24>; + clocks = <&clk IMX8MP_CLK_USB_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "usb", "pcie"; + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, + <&pgc_usb1_phy>, <&pgc_usb2_phy>, + <&pgc_hsiomix>, <&pgc_pcie_phy>; + power-domain-names = "bus", "usb", "usb-phy1", + "usb-phy2", "pcie", "pcie-phy"; + #power-domain-cells = <1>; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -865,17 +926,20 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; #phy-cells = <0>; status = "disabled"; }; usb3_0: usb@32f10100 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10100 0x8>; + reg = <0x32f10100 0x8>, + <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = ; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; @@ -907,16 +971,20 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; #phy-cells = <0>; + status = "disabled"; }; usb3_1: usb@32f10108 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10108 0x8>; + reg = <0x32f10108 0x8>, + <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = ; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; -- 2.35.1