From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A72ACC433EF for ; Sat, 2 Apr 2022 22:17:54 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9DE0F839BE; Sun, 3 Apr 2022 00:17:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="u31DLAmm"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 408D3839AA; Sun, 3 Apr 2022 00:17:27 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E0FF383970 for ; Sun, 3 Apr 2022 00:17:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 94E1660F2F; Sat, 2 Apr 2022 22:17:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D763CC340F3; Sat, 2 Apr 2022 22:17:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1648937838; bh=o/PECdKpOIc4D9vmgxgJbqdC9AVOxYkVeij1Aa6Fy48=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u31DLAmmLRHmTTwcwJoSyuIFi1Bwzfg7zy1aTQoYXJ6I/JmV1Ixyk2Za2isEtqUta uhFsWc94Jl509snHDXyK1jWePtCjvL/+K5+lQJdaoDfvzkfxGvpPmMNwArg/objdvr f5tSXGHIB/MB38JvQE3uKmbLEGg8quYeuxQucBPfA5XIfaYPmg7qfeu1qtAp72I9sr NdbITNofsvnz2miM7i0rnYbqKMlfxsMWyv5kt1s4CDFw0Fvm9Cfrswf17LNq9nsFpC eC2mL/wZDOVgr9YrKco3ipg9LytI4woM6wrNl6NRVAW/nALoFqaRc0QL4ZLoF2R9cg pR/TUr3SCMsrg== Received: by pali.im (Postfix) id 0B7661640; Sun, 3 Apr 2022 00:17:15 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Peng Fan , Jaehoon Chung Cc: u-boot@lists.denx.de Subject: [PATCH 2/3] mmc: fsl_esdhc_spl: pre-PBL: fix determining U-Boot size Date: Sun, 3 Apr 2022 00:17:00 +0200 Message-Id: <20220402221701.18498-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402221701.18498-1-pali@kernel.org> References: <20220402221701.18498-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean In pre-PBL header is stored size of code which BootROM copies from SD card to L2/SRAM. This size has upper limit of L2 cache size. In most cases this is size of U-Boot SPL or size of L2 cache. Therefore this size in pre-PBL header cannot be used for determining size of proper U-Boot. So always use CONFIG_SYS_MMC_U_BOOT_SIZE for determining size of proper U-Boot which stored on SD card. Signed-off-by: Pali Rohár --- drivers/mmc/fsl_esdhc_spl.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 109f558dcad3..b87597a88e1d 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -79,7 +79,6 @@ void __noreturn mmc_boot(void) #ifdef CONFIG_FSL_CORENET offset = CONFIG_SYS_MMC_U_BOOT_OFFS; - code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; #else blklen = mmc->read_bl_len; tmp_buf = malloc(blklen); @@ -135,18 +134,11 @@ void __noreturn mmc_boot(void) offset = (offset << 8) + val; } offset += CONFIG_SYS_MMC_U_BOOT_OFFS; - /* Get the code size from offset 0x48 */ - byte_num = 4; - code_len = 0; - for (i = 0; i < byte_num; i++) { - val = *(tmp_buf + ESDHC_BOOT_IMAGE_SIZE + i); - code_len = (code_len << 8) + val; - } - code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS; +#endif /* * Load U-Boot image from mmc into RAM */ -#endif + code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, -- 2.20.1