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[2603:6081:7b01:cbda:2ef0:5dff:fedb:a8ba]) by smtp.gmail.com with ESMTPSA id n10-20020a05622a040a00b002e315b9f08asm5392376qtx.35.2022.04.02.17.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 17:16:39 -0700 (PDT) Date: Sat, 2 Apr 2022 20:16:37 -0400 From: Tom Rini To: Sean Anderson Cc: Linus Walleij , Liviu Dudau , Andre Przywara , Simon Glass , u-boot@lists.denx.de Subject: Re: [PATCH v3 23/29] arm64: Catch non-emulated semihosting calls Message-ID: <20220403001637.GF14476@bill-the-cat> References: <20220322205938.1721846-1-sean.anderson@seco.com> <20220322205938.1721846-24-sean.anderson@seco.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="fy3IkwjgC3G0yg4I" Content-Disposition: inline In-Reply-To: <20220322205938.1721846-24-sean.anderson@seco.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean --fy3IkwjgC3G0yg4I Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Mar 22, 2022 at 04:59:31PM -0400, Sean Anderson wrote: > If a debugger is not attached to U-Boot, semihosting calls will raise a > synchronous abort exception. Try to catch this and disable semihosting > so we can e.g. use another uart if one is available. In the immediate > case, we return an error, since it is not always possible to check for > semihosting beforehand (debug uart, user-initiated load command, etc.) >=20 > We handle all possible semihosting instructions, which is probably > overkill. However, we do need to keep track of what instruction set > we're using so that we don't suppress an actual error. >=20 > A future enhancement could try to determine semihosting capability by > inspecting the processor state. There's an example of this at [1] for > RISC-V. The equivalent for ARM would inspect the monitor modei > enable/select bits of the DSCR. However, as the article notes, an > exception handler is still helpful in order to catch disconnected > debuggers. >=20 > [1] https://tomverbeure.github.io/2021/12/30/Semihosting-on-RISCV.html#av= oiding-hangs-when-a-debugger-is-not-connected >=20 > Signed-off-by: Sean Anderson Applied to u-boot/next, thanks! --=20 Tom --fy3IkwjgC3G0yg4I Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmJI52UACgkQFHw5/5Y0 tyw64Av8D8b0CLWFpGlC4DRhRzrDhSqOMuWG/U/AO3RoMSbKBfrHU615Rmhtelz2 c8VCbepludjW47u+qcj0xVHOTE6E1uR9qVmcgEjZH9duHh2zI16Rw5Mk9mA4v+dc JuKIr9KpiY6YIP2mZs95rQ4gHZ7eBRW5nKnkeTh2GzKa7VmNmdw6i93UnBYOSDnM kASgGteLTDevN4Bvvk1CJDq6e8YTpeqX4qp0L7V4lhjmfuvWy59n6djF5xAvVUV+ v6pk9kH4UNnUeCSjaNSf3znUu3AQJ8LUXi1RaMUwpJlEo0LCOlx4kpzNls427mzy /GHW5TSbxRN6D0ptRiwQQLt1o4kfrBbPSVmTg7g0wyibMCqkQAPWAVmTkd/uAgqV 2/Infw5sgUnILQqFd3qyN/zGCRCWnm1FcK5dIahixVMLmCJ/HF+qBWqYHR1VxAom CKkhO3JRkjIswElIGXE6wT+9Ezo5B91wxkfgt+xTB7+BHejk8zXIYkWybpeOrLKV spnTuYT5 =DYbx -----END PGP SIGNATURE----- --fy3IkwjgC3G0yg4I--