From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB808C433EF for ; Tue, 5 Apr 2022 13:43:11 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7EFC883AF5; Tue, 5 Apr 2022 15:42:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="pRGxgSMf"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0A87883B10; Tue, 5 Apr 2022 15:42:51 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8C91583B32 for ; Tue, 5 Apr 2022 15:42:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 4379AB818B8; Tue, 5 Apr 2022 13:42:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D8C31C385A1; Tue, 5 Apr 2022 13:42:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649166164; bh=L9dqSGTXt+U3jnpgqXO3EgxsRkX//IBCKW1fxUSB4fc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pRGxgSMfNL2WT27xQox//kGYEFagnA+1akgpTG6H3V7gf499Ui7yNVOliStduwOgs 25xy2zFpyh3EZ5dXix7Jef5CiCmuV80DVOrGWxLjOr1erh9Dc3T3Bvy7P6wE+Sdfps 4mW1XnsaJ4ft73RsaxSxYOhT/oJahvQl0k5B6RnLGHU7s2KD2Eux4SKAsUYNqXTTYw DxfbrQRZ/6sYMFx7qbaSGW0gTp7WGpONWDo0O5/J1uJKCY6qQmcDdpTY7ueLlK8dtg v7n9m8r9SY52qx+KgMRwaZqSNnoR6UvBo+XMTVZgVIl8mgKz+YojwBwvvl5hZe4+vJ YRGTxmvTpMeKw== Received: by pali.im (Postfix) id 0B8294A23; Tue, 5 Apr 2022 15:42:41 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Qiang Zhao , Shengzhou Liu , Alexander Graf , Bin Meng , Wolfgang Denk , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 2/2] board: freescale: p1_p2_rdb_pc: Calculate offsets for eSDHC boot sector Date: Tue, 5 Apr 2022 15:40:32 +0200 Message-Id: <20220405134032.704-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220405134032.704-1-pali@kernel.org> References: <20220405134032.704-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Correctly calculate offsets between SPL and proper U-Boot when new config option CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR for generating eSDHC boot sector is enabled. Otherwise SPL would not be able to boot proper U-Boot. Signed-off-by: Pali Rohár --- include/configs/p1_p2_rdb_pc.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 0d1cc218fac0..370772053e63 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -73,11 +73,16 @@ #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_PAD_TO 0x20000 +#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) +#else #define CONFIG_SPL_MAX_SIZE CONFIG_SPL_PAD_TO +#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#endif #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_MPC85XX_NO_RESETVEC #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_COMMON_INIT_DDR -- 2.20.1