From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E9F5C433EF for ; Tue, 5 Apr 2022 23:03:23 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 620D083C09; Wed, 6 Apr 2022 01:02:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2EE2183C59; Wed, 6 Apr 2022 01:02:49 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 41D3A83ADC for ; Wed, 6 Apr 2022 01:02:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AA0CD1424; Tue, 5 Apr 2022 16:02:34 -0700 (PDT) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0C08C3F718; Tue, 5 Apr 2022 16:02:33 -0700 (PDT) Date: Tue, 5 Apr 2022 23:37:18 +0100 From: Andre Przywara To: Angelo Dureghello Cc: jagan@amarulasolutions.com, trini@konsulko.com, u-boot@lists.denx.de Subject: Re: [PATCH 2/2] sunxi: fix non working console on uart2 Message-ID: <20220405233718.20abff40@slackpad.lan> In-Reply-To: <20211009121859.1384658-2-angelo.dureghello@timesys.com> References: <20211009121859.1384658-1-angelo.dureghello@timesys.com> <20211009121859.1384658-2-angelo.dureghello@timesys.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Sat, 9 Oct 2021 14:18:59 +0200 Angelo Dureghello wrote: > Fix non working console on uart2, that seems releated to both > Allwinner H2+ and H3. > > Signed-off-by: Angelo Dureghello Dropped CONFIG_MACH_SUN8I_H2_PLUS, reordered as suggested in the other reply, and applied to sunxi/master. Thanks! Andre > --- > arch/arm/include/asm/arch-sunxi/gpio.h | 1 + > arch/arm/mach-sunxi/board.c | 10 +++++++++- > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h > index 2969a530ae..21fcfd5638 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -150,6 +150,7 @@ enum sunxi_gpio_number { > #define SUN7I_GPA_GMAC 5 > #define SUN6I_GPA_SDC2 5 > #define SUN6I_GPA_SDC3 4 > +#define SUN8I_GPA_UART2 2 > #define SUN8I_H3_GPA_UART0 2 > > #define SUN4I_GPB_PWM 2 > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c > index adb63e93e7..623da744e2 100644 > --- a/arch/arm/mach-sunxi/board.c > +++ b/arch/arm/mach-sunxi/board.c > @@ -145,10 +145,18 @@ static int gpio_init(void) > sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); > sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); > sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); > -#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) > +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) && \ > + !defined(CONFIG_MACH_SUN8I_H2_PLUS) && \ > + !defined(CONFIG_MACH_SUN8I_H3) > sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); > sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); > sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); > +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) && \ > + (defined(CONFIG_MACH_SUN8I_H2_PLUS) || \ > + defined(CONFIG_MACH_SUN8I_H3)) > + sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_GPA_UART2); > + sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_GPA_UART2); > + sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP); > #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) > sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); > sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);