From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8DF6C433EF for ; Thu, 7 Apr 2022 07:28:50 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EB89683DD3; Thu, 7 Apr 2022 09:28:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1649316523; bh=LoqX4hyQlcobtx3Ff+1ij7rIP72MExyiJ7kETmzDGl4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Mbd8xOVRzFSx5v7DtcRCu+tGQo0wRLX429dzQNdhYyL1VWaxx7Ivm+ji6zoERJFwD WtzcJbpNoJWLuG6XH4KBBK9oR94jNH2Z4nYHVkfARsebX+Ske7fLBjRMzzlfCuNPGf amiiSFF4PQyLi8++Sjma8VKJmhHtZT1bSVXrQ7ib3wmte1WctxZAucIAq6Eom3kV12 MuEuX+c2ldVbSJhnDILxvOya9lMyvhp95k2HNU6G2YUduKj9WKwGEY7Juw37Ktq3x5 +HmuzTVxb3MKMl/l8aKueDNSsgnCLq97iLDs94GRxE1FsB88fpKGRSI53yuj2hS0Nh 5kT9b+zm+bLzQ== Received: by phobos.denx.de (Postfix, from userid 109) id 7A80E83D95; Thu, 7 Apr 2022 09:23:14 +0200 (CEST) Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [91.198.250.253]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1AD8A83C67 for ; Thu, 7 Apr 2022 09:12:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp2.mailbox.org (unknown [91.198.250.124]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4KYsyP6WMsz9sZd; Thu, 7 Apr 2022 09:12:13 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com Subject: [PATCH v2 45/52] mips: octeon: cpu.c: Implement configure_lmtdma_window() Date: Thu, 7 Apr 2022 09:11:47 +0200 Message-Id: <20220407071154.51997-46-sr@denx.de> In-Reply-To: <20220407071154.51997-1-sr@denx.de> References: <20220407071154.51997-1-sr@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Import configure_lmtdma_window from Marvell 2013 U-Boot as it's needed for network functionality. Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/cpu.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c index fffd9dfb8580..1bdc6cd72903 100644 --- a/arch/mips/mach-octeon/cpu.c +++ b/arch/mips/mach-octeon/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020 Marvell International Ltd. + * Copyright (C) 2020-2022 Marvell International Ltd. */ #include @@ -17,6 +17,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -393,6 +395,33 @@ static int init_bootcmd_console(void) return ret; } +static void configure_lmtdma_window(void) +{ + u64 tmp; + u64 addr; + u64 end_addr; + + CVMX_MF_CVM_MEM_CTL(tmp); + tmp &= ~0x1ffull; + tmp |= 0x104ull; + + /* enable LMTDMA */ + tmp |= (1ull << 51); + /* configure scratch line 2 for LMT */ + /* TODO: reserve this scratch line, so that others will not use it */ + /* TODO: store LMTLINE in global var */ + tmp |= (CVMX_PKO_LMTLINE << 45); + /* clear LMTLINE in scratch */ + addr = CVMX_PKO_LMTLINE * CVMX_CACHE_LINE_SIZE; + end_addr = addr + CVMX_CACHE_LINE_SIZE; + + while (addr < end_addr) { + *CASTPTR(volatile u64, addr + CVMX_SCRATCH_BASE) = (u64)0; + addr += 8; + } + CVMX_MT_CVM_MEM_CTL(tmp); +} + int arch_early_init_r(void) { int ret; @@ -405,6 +434,9 @@ int arch_early_init_r(void) if (ret) return ret; + if (octeon_has_feature(OCTEON_FEATURE_PKO3)) + configure_lmtdma_window(); + return 0; } -- 2.35.1