From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1EE32C433EF for ; Thu, 7 Apr 2022 09:32:37 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 087CF83BC7; Thu, 7 Apr 2022 11:32:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="I3NXwoEv"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0C75483BBE; Thu, 7 Apr 2022 11:32:33 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9B930820F5 for ; Thu, 7 Apr 2022 11:32:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EA9E661AA9; Thu, 7 Apr 2022 09:32:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0A788C385A4; Thu, 7 Apr 2022 09:32:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649323947; bh=2wntnNPy+1qUYAULT0GsfoMKPVDjLKLSQyiS0K3fYw0=; h=From:To:Cc:Subject:Date:From; b=I3NXwoEvBqTfl7SzDN3Nn/1xLBSQUdIfi14FctRUChpl1pFVTxMQYE6caTJR8Gzv/ Cq1YtzHUd1lwXL4z0mwGa7nm28+kMC9OOeTTtFP3MFiqlJZTMqEOPZus+I4GZEhR1y UN+CTnZGmndC98VYzhXj/U972yDEGNHLZrvVq3cLkBHYN8uyehIPsrXx1BTgDSZKEa 3iVsBQHSrnBIl8dQ7vliHF9/zwQHtNHHorI+L+CdjYp2bqc/RGb/mXf+l8SamsmDVj QAATwa6enZc6SfTl4Jlezn0o9u4v3MK131bQ3r3zMVbi0u5qog2fpCURDFZctEhSec EBAAVJiANnOPQ== Received: by pali.im (Postfix) id 3B52A7E4; Thu, 7 Apr 2022 11:32:24 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Konstantin Porotchkin , Vladimir Vid , Robert Marko Cc: u-boot@lists.denx.de Subject: [PATCH] arm: mvebu: a37xx: Add support for writing Security OTP values Date: Thu, 7 Apr 2022 11:32:10 +0200 Message-Id: <20220407093210.10590-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Implement write support for Security OTP values via mailbox API commands MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE. Write support for North and South Bridge OTPs are not implemented as these OTPs are already burned in factory with some data. Signed-off-by: Pali Rohár --- This patch depends on series which implements read support for A3720 OTP: https://patchwork.ozlabs.org/project/uboot/list/?series=287578&state=* Stefan, what do you think, should be enable write support by default. Or should it be hidden under some other CONFIG option? Becaue currently CONFIG_CMD_FUSE enable both read and write support (or what driver implements). --- arch/arm/mach-mvebu/armada3700/efuse.c | 50 ++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c index 50c73f36c565..07d5f394354c 100644 --- a/arch/arm/mach-mvebu/armada3700/efuse.c +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -113,6 +113,41 @@ static int rwtm_otp_read(u8 row, u32 word, u32 *data) return res; } +static int rwtm_otp_write(u8 row, u32 word, u32 data) +{ + u32 in[4]; + int res = -EINVAL; + + if (word < 2) { + /* + * MBOX_CMD_OTP_WRITE_32B command is supported by Marvell + * fuse.bin firmware and also by new CZ.NIC wtmi firmware. + * This command writes only selected bits to OTP and does + * not calculate ECC bits. It does not allow to write the + * lock bit. + */ + in[0] = row; + in[1] = word * 32; + in[2] = data; + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0); + } else if (word == 2 && !(data & ~0x1)) { + /* + * MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC + * wtmi firmware and allows to write any bit to OTP, including + * the lock bit. It does not calculate or write ECC bits too. + * For compatibility with Marvell fuse.bin firmware, use this + * command only for writing the lock bit. + */ + in[0] = row; + in[1] = 0; + in[2] = 0; + in[3] = data; + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0); + } + + return res; +} + /* * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2) * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2) @@ -154,8 +189,19 @@ int fuse_read(u32 bank, u32 word, u32 *val) int fuse_prog(u32 bank, u32 word, u32 val) { - /* TODO: not implemented yet */ - return -ENOSYS; + if (bank <= RWTM_MAX_BANK) { + if (word >= RWTM_ROW_WORDS) + return -EINVAL; + return rwtm_otp_write(bank, word, val); + } else if (bank == OTP_NB_BANK) { + /* TODO: not implemented yet */ + return -ENOSYS; + } else if (bank == OTP_SB_BANK) { + /* TODO: not implemented yet */ + return -ENOSYS; + } else { + return -EINVAL; + } } int fuse_sense(u32 bank, u32 word, u32 *val) -- 2.20.1