From: "Pali Rohár" <pali@kernel.org>
To: Priyanka Jain <priyanka.jain@nxp.com>,
Qiang Zhao <qiang.zhao@nxp.com>,
Shengzhou Liu <Shengzhou.Liu@nxp.com>,
Sinan Akman <sinan@writeme.com>
Cc: u-boot@lists.denx.de
Subject: [PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h
Date: Thu, 7 Apr 2022 12:16:23 +0200 [thread overview]
Message-ID: <20220407101624.15850-11-pali@kernel.org> (raw)
In-Reply-To: <20220407101624.15850-1-pali@kernel.org>
Code for changing BootROM source is platform generic and can be used by any
P1* and P2* compatible board. Not only by RDB boards which use config
header file p1_p2_rdb_pc.h.
So move this code from p1_p2_rdb_pc.h to p1_p2_bootrom.h and cleanup macros
for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
This allows to use code for changing BootROM source also by other boards in
future.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
include/configs/p1_p2_bootrom.h | 32 +++++++++++++++
include/configs/p1_p2_rdb_pc.h | 73 +++++++++++++++++++++------------
2 files changed, 78 insertions(+), 27 deletions(-)
create mode 100644 include/configs/p1_p2_bootrom.h
diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h
new file mode 100644
index 000000000000..a1f61b788cf7
--- /dev/null
+++ b/include/configs/p1_p2_bootrom.h
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) 2022 Pali Rohár <pali@kernel.org>
+
+#define CHANGE_BOOTROM_SOURCE_CMD(SOURCE, MASK) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 SOURCE 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 MASK 1
+
+#ifdef __SW_NOR_BANK_LO
+#define CHANGE_BOOTROM_LOWER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_NOR_BANK_UP
+#define CHANGE_BOOTROM_UPPER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_BOOT_NOR
+#define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_SPI
+#define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_SD
+#define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_NAND
+#define CHANGE_BOOTROM_SOURCE_NAND_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_PCIE
+#define CHANGE_BOOTROM_SOURCE_PCIE_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)
+#endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 995bd983cef1..d41b31081017 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -79,6 +79,8 @@
*/
#endif
+#include "p1_p2_bootrom.h"
+
#ifdef CONFIG_SDCARD
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
@@ -575,30 +577,46 @@
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#ifdef __SW_BOOT_NOR
-#define __NOR_RST_CMD \
-norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+#ifdef CHANGE_BOOTROM_LOWER_NOR_BANK_CMD
+#define __MAP_NOR_LOWER_CMD "map_lowernorbank="__stringify(CHANGE_BOOTROM_LOWER_NOR_BANK_CMD)"\0"
+#else
+#define __MAP_NOR_LOWER_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_UPPER_NOR_BANK_CMD
+#define __MAP_NOR_UPPER_CMD "map_uppernorbank="__stringify(CHANGE_BOOTROM_UPPER_NOR_BANK_CMD)"\0"
+#else
+#define __MAP_NOR_UPPER_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD
+#define __NOR_RST_CMD "norboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD)"; reset\0"
+#else
+#define __NOR_RST_CMD ""
#endif
-#ifdef __SW_BOOT_SPI
-#define __SPI_RST_CMD \
-spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD
+#define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; reset\0"
+#else
+#define __SPI_RST_CMD ""
#endif
-#ifdef __SW_BOOT_SD
-#define __SD_RST_CMD \
-sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_SD_CMD
+#define __SD_RST_CMD "sdboot="__stringify(CHANGE_BOOTROM_SOURCE_SD_CMD)"; reset\0"
+#else
+#define __SD_RST_CMD ""
#endif
-#ifdef __SW_BOOT_NAND
-#define __NAND_RST_CMD \
-nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD
+#define __NAND_RST_CMD "nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0"
+#else
+#define __NAND_RST_CMD ""
#endif
-#ifdef __SW_BOOT_PCIE
-#define __PCIE_RST_CMD \
-pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_PCIE_CMD
+#define __PCIE_RST_CMD "pciboot="__stringify(CHANGE_BOOTROM_SOURCE_PCIE_CMD)"; reset\0"
+#else
+#define __PCIE_RST_CMD ""
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -626,13 +644,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
"nandfdtaddr=80000\0" \
"ramdisk_size=120000\0" \
__VSCFW_ADDR \
-"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-__stringify(__NOR_RST_CMD)"\0" \
-__stringify(__SPI_RST_CMD)"\0" \
-__stringify(__SD_RST_CMD)"\0" \
-__stringify(__NAND_RST_CMD)"\0" \
-__stringify(__PCIE_RST_CMD)"\0"
+__MAP_NOR_LOWER_CMD \
+__MAP_NOR_UPPER_CMD \
+__NOR_RST_CMD \
+__SPI_RST_CMD \
+__SD_RST_CMD \
+__NAND_RST_CMD \
+__PCIE_RST_CMD \
+""
#define CONFIG_USB_FAT_BOOT \
"setenv bootargs root=/dev/ram rw " \
--
2.20.1
next prev parent reply other threads:[~2022-04-07 10:19 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
2022-04-07 10:16 ` [PATCH 01/11] board: freescale: p1_p2_rdb_pc: Do not hang in checkboard() Pali Rohár
2022-04-07 10:16 ` [PATCH 02/11] board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations Pali Rohár
2022-04-07 10:16 ` [PATCH 03/11] board: freescale: p1_p2_rdb_pc: Fix parsing negated upper 4 bits from boot input data Pali Rohár
2022-04-25 14:12 ` [PATCH v2] board: freescale: p1_p2_rdb_pc: Fix parsing inverted " Pali Rohár
2022-06-16 9:00 ` Peng Fan (OSS)
2022-06-16 12:37 ` [PATCH v3] " Pali Rohár
2022-06-23 13:04 ` Pali Rohár
2022-07-03 12:39 ` Pali Rohár
2022-07-08 22:49 ` Pali Rohár
2022-07-08 23:10 ` Tom Rini
2022-07-23 9:48 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 04/11] board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit when SDHC_WP is used as GPIO Pali Rohár
2022-04-07 10:16 ` [PATCH 05/11] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map Pali Rohár
2022-04-07 10:16 ` [PATCH 06/11] board: freescale: p1_p2_rdb_pc: Move ifdef for USB/eLBC check to correct place Pali Rohár
2022-04-07 10:16 ` [PATCH 07/11] board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr Pali Rohár
2022-04-07 10:16 ` [PATCH 08/11] board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and address Pali Rohár
2022-04-07 10:16 ` [PATCH 09/11] board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks Pali Rohár
2022-04-07 10:16 ` Pali Rohár [this message]
2022-04-25 14:48 ` [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h Pali Rohár
2022-05-26 6:08 ` Priyanka Jain (OSS)
2022-05-26 8:32 ` Pali Rohár
2022-05-26 8:52 ` [PATCH v3] " Pali Rohár
2022-06-02 22:02 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 11/11] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot Pali Rohár
2022-04-25 14:50 ` [PATCH v2] " Pali Rohár
2022-06-16 9:01 ` Peng Fan (OSS)
2022-06-23 13:43 ` Pali Rohár
2022-07-03 12:38 ` Pali Rohár
[not found] ` <20220708224344.jswbjxp3tdnfnmlp@pali>
2022-07-08 23:12 ` Tom Rini
2022-07-21 22:20 ` Pali Rohár
2022-08-01 13:01 ` Pali Rohár
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