From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00DD2C433F5 for ; Thu, 7 Apr 2022 10:18:47 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1C51F83CA4; Thu, 7 Apr 2022 12:18:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="Y80md6fE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B63C083CF3; Thu, 7 Apr 2022 12:17:51 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A945F83C97 for ; Thu, 7 Apr 2022 12:17:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4973B61D3B; Thu, 7 Apr 2022 10:17:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7228AC385AA; Thu, 7 Apr 2022 10:17:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649326661; bh=apcvM6L9uxQpLjTVmXYu03AD7sQDbRr7zB9iPcaB/a8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y80md6fEgFfy4PkLfKfPL1EAQ6tqqowAqaYYE/ZvUwMaa2C64ia+yGbm76/lYccqC Oy+CR463SHJPFBCOxlyMQFqkMuM5VFkcjq8QYJH0q6lfOGmahk3kEKKT6EaYzezmDG IFeEynKR/+2PvgonRZYqQcKDDyF+OcYsL2j+nHqTKTLjJT+BwlpZFLm2s1H/CcuhaJ tZKZYNY4wQ9QBds+oqOHUamavaO5gRvU8clLEzGdNS09Q/c/cbgpMqF3j7PK2/esMp MapGgZHsWlDTH7/T6NRZQMFWF7lcX8Q5Zi6+4S/9NkTLm7NbKkA2mwl0k//wSgAfe6 UrxhE6VuLYGwg== Received: by pali.im (Postfix) id EE933BDD; Thu, 7 Apr 2022 12:17:38 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Qiang Zhao , Shengzhou Liu , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 04/11] board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit when SDHC_WP is used as GPIO Date: Thu, 7 Apr 2022 12:16:17 +0200 Message-Id: <20220407101624.15850-5-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220407101624.15850-1-pali@kernel.org> References: <20220407101624.15850-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean When MPC85xx_PMUXCR_SDHC_WP is set then SDHC controller automatically makes inserted SD card readonly if GPIO[9] is active. In some design GPIO[9] pin does not have to be connected to SD card write-protect pin and can be used as GPIO. So do not set MPC85xx_PMUXCR_SDHC_WP bit when GPIO[9] is not used for SDHC_WP functionality. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 766a82386079..fc581bdb2a40 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -147,8 +147,10 @@ int board_early_init_f(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD); +#ifndef SDHC_WP_IS_GPIO + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP); +#endif clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); -- 2.20.1