From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 467EDC433EF for ; Thu, 7 Apr 2022 10:19:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C011983D96; Thu, 7 Apr 2022 12:18:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="ZKmwSgt4"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D0AFA83CD8; Thu, 7 Apr 2022 12:17:52 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7EDC783C67 for ; Thu, 7 Apr 2022 12:17:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8AB6861D47; Thu, 7 Apr 2022 10:17:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A99A3C385A6; Thu, 7 Apr 2022 10:17:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649326660; bh=HXg9J0qii8bIiR0gUTN8qDtKdk6lDFrom6xaGkrkQY4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZKmwSgt4KYf99SMMhFHnf3CkDU49vEHJ8Zhy0lpLkMgRUy/Hl2HPAcOSu5Bs5XIPE J27y7Qkn04mfdhIfru/s55SP05WWgCuDAV+Kn2Rqsqw1KcAFHfpI/4reoOlUt20vga uNYt7IuHG4p3dWS/tKzlrnWgSTP/WxkbPj8wq6xuvanSMlMKnmf3pSMyfrR57JCnbN bCIdELZ4hE2n3g6gRJP7F+32ho4amfm8xU+XVt1uBgD8zyq53wKKmlFk3qhG+gHr/1 GqUTi+9V0O0hstDFfi97t+j7Ws4ObPrQ5loLcbUQzlSAUhGLgz6kybfBhE+VHnlfNj TgLKUeLgygLcw== Received: by pali.im (Postfix) id 63AFFC77; Thu, 7 Apr 2022 12:17:39 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Qiang Zhao , Shengzhou Liu , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 05/11] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map Date: Thu, 7 Apr 2022 12:16:18 +0200 Message-Id: <20220407101624.15850-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220407101624.15850-1-pali@kernel.org> References: <20220407101624.15850-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded attribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and also allow speculative loading (by not setting Guarded attribute). Also enable Memory Coherency attribute for second 1G SDRAM map. In commit 316f0d0f8f3c ("powerpc: mpc85xx: Fix static TLB table for SDRAM") it was enabled for all SDRAM maps on all other boards, just missed this one case. As a last thing, first 1G SDRAM map has wrong comment, so adjust it. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/tlb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index fcd7a55199f0..5931ec650bd8 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -79,16 +79,16 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_SYS_RAMBOOT) || \ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) - /* *I*G - eSDHC/eSPI/NAND boot */ + /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #if defined(CONFIG_TARGET_P1020RDB_PD) - /* 2G DDR on P1020MBG, map the second 1G */ + /* **M** - 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 9, BOOKE_PAGESZ_1G, 1), #endif #endif /* RAMBOOT/SPL */ -- 2.20.1