From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D4EBC433EF for ; Thu, 7 Apr 2022 11:58:43 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 860EC83DA3; Thu, 7 Apr 2022 13:58:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=nic.cz Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="I5ODu9KL"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0882483DAF; Thu, 7 Apr 2022 13:58:40 +0200 (CEST) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8EAF183DA3 for ; Thu, 7 Apr 2022 13:58:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=nic.cz Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=marek.behun@nic.cz Received: from thinkpad (unknown [172.20.6.87]) by mail.nic.cz (Postfix) with ESMTPS id E3B8813FCA1; Thu, 7 Apr 2022 13:58:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1649332716; bh=kquokMivSUBYHIAOEvUaZXApGgSkgp9hjZmrdnj2fkI=; h=Date:From:To:Cc:Subject:From; b=I5ODu9KLaUAgQPLv9G+6eoOkF0jr8/ikVjJp/8FadHXQimOMMtW7PxQOMIKsuTx8n 93WfUmd7T8JbTNF9/4DZ2Z0p3tnGFTtvx3zfUTldyEwfEJpJUl9tcH2zZbhNoJek+a pWGzxf1nyeNQSkCG03NZ0Sw70H0XMPB+vFH3aZrk= Date: Thu, 7 Apr 2022 13:58:34 +0200 From: Marek =?UTF-8?B?QmVow7pu?= To: Pali =?UTF-8?B?Um9ow6Fy?= Cc: Stefan Roese , Konstantin Porotchkin , Vladimir Vid , Robert Marko , u-boot@lists.denx.de Subject: Re: [PATCH] arm: mvebu: a37xx: Add support for writing Security OTP values Message-ID: <20220407135834.2a477fc7@thinkpad> In-Reply-To: <20220407093210.10590-1-pali@kernel.org> References: <20220407093210.10590-1-pali@kernel.org> X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Thu, 7 Apr 2022 11:32:10 +0200 Pali Roh=C3=A1r wrote: > Implement write support for Security OTP values via mailbox API commands > MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE. >=20 > Write support for North and South Bridge OTPs are not implemented as these > OTPs are already burned in factory with some data. >=20 > Signed-off-by: Pali Roh=C3=A1r > --- > This patch depends on series which implements read support for A3720 OTP: > https://patchwork.ozlabs.org/project/uboot/list/?series=3D287578&state=3D* >=20 > Stefan, what do you think, should be enable write support by default. Or > should it be hidden under some other CONFIG option? Becaue currently > CONFIG_CMD_FUSE enable both read and write support (or what driver > implements). > --- > arch/arm/mach-mvebu/armada3700/efuse.c | 50 ++++++++++++++++++++++++-- > 1 file changed, 48 insertions(+), 2 deletions(-) >=20 > diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu= /armada3700/efuse.c > index 50c73f36c565..07d5f394354c 100644 > --- a/arch/arm/mach-mvebu/armada3700/efuse.c > +++ b/arch/arm/mach-mvebu/armada3700/efuse.c > @@ -113,6 +113,41 @@ static int rwtm_otp_read(u8 row, u32 word, u32 *data) > return res; > } > =20 > +static int rwtm_otp_write(u8 row, u32 word, u32 data) > +{ > + u32 in[4]; > + int res =3D -EINVAL; > + > + if (word < 2) { > + /* > + * MBOX_CMD_OTP_WRITE_32B command is supported by Marvell > + * fuse.bin firmware and also by new CZ.NIC wtmi firmware. > + * This command writes only selected bits to OTP and does > + * not calculate ECC bits. It does not allow to write the > + * lock bit. > + */ > + in[0] =3D row; > + in[1] =3D word * 32; > + in[2] =3D data; > + res =3D mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0); > + } else if (word =3D=3D 2 && !(data & ~0x1)) { > + /* > + * MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC > + * wtmi firmware and allows to write any bit to OTP, including > + * the lock bit. It does not calculate or write ECC bits too. > + * For compatibility with Marvell fuse.bin firmware, use this > + * command only for writing the lock bit. > + */ > + in[0] =3D row; > + in[1] =3D 0; > + in[2] =3D 0; > + in[3] =3D data; > + res =3D mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0); > + } > + > + return res; > +} > + > /* > * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits = via 44 banks and words 0-2) > * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2) > @@ -154,8 +189,19 @@ int fuse_read(u32 bank, u32 word, u32 *val) > =20 > int fuse_prog(u32 bank, u32 word, u32 val) > { > - /* TODO: not implemented yet */ > - return -ENOSYS; > + if (bank <=3D RWTM_MAX_BANK) { > + if (word >=3D RWTM_ROW_WORDS) > + return -EINVAL; > + return rwtm_otp_write(bank, word, val); > + } else if (bank =3D=3D OTP_NB_BANK) { > + /* TODO: not implemented yet */ > + return -ENOSYS; > + } else if (bank =3D=3D OTP_SB_BANK) { > + /* TODO: not implemented yet */ > + return -ENOSYS; > + } else { > + return -EINVAL; > + } > } > =20 > int fuse_sense(u32 bank, u32 word, u32 *val) Reviewed-by: Marek Beh=C3=BAn