* [PATCH 01/10] net: Remove armada100_fec driver
@ 2022-03-31 17:46 Tom Rini
2022-03-31 17:46 ` [PATCH 02/10] net: Remove ax88180 driver Tom Rini
` (9 more replies)
0 siblings, 10 replies; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
This driver is not enabled by any board and not converted to DM_ETH.
Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/net/Makefile | 1 -
drivers/net/armada100_fec.c | 739 ------------------------------------
drivers/net/armada100_fec.h | 208 ----------
3 files changed, 948 deletions(-)
delete mode 100644 drivers/net/armada100_fec.c
delete mode 100644 drivers/net/armada100_fec.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a6d0c23f02d3..b57149b33994 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -6,7 +6,6 @@
obj-$(CONFIG_AG7XXX) += ag7xxx.o
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
-obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o
obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
deleted file mode 100644
index 5d4b90c6ba72..000000000000
--- a/drivers/net/armada100_fec.c
+++ /dev/null
@@ -1,739 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/types.h>
-#include <asm/byteorder.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/mii.h>
-#include <asm/io.h>
-#include <asm/arch/armada100.h>
-#include "armada100_fec.h"
-
-#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
-
-#ifdef DEBUG
-static int eth_dump_regs(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- unsigned int i = 0;
-
- printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
- printf("offset: smi, value: 0x%x\n", readl(®s->smi));
- for (i = 0x400; i <= 0x4e4; i += 4)
- printf("offset: 0x%x, value: 0x%x\n",
- i, readl(ARMD1_FEC_BASE + i));
- return 0;
-}
-#endif
-
-static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
-{
- u32 timeout = PHY_WAIT_ITERATIONS;
- u32 reg_val;
-
- while (--timeout) {
- reg_val = readl(reg);
- if (cond && (reg_val & flag))
- break;
- else if (!cond && !(reg_val & flag))
- break;
- udelay(PHY_WAIT_MICRO_SECONDS);
- }
- return !timeout;
-}
-
-static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad,
- int phy_reg)
-{
- u16 value = 0;
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- u32 val;
-
- if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
- val = readl(®s->phyadr);
- value = val & 0x1f;
- return value;
- }
-
- /* check parameters */
- if (phy_addr > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
- __func__, phy_addr);
- return -EINVAL;
- }
- if (phy_reg > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
- __func__, phy_reg);
- return -EINVAL;
- }
-
- /* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
- printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
- return -1;
- }
-
- writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
-
- /* now wait for the data to be valid */
- if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) {
- val = readl(®s->smi);
- printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
- __func__, val);
- return -1;
- }
- val = readl(®s->smi);
- value = val & 0xffff;
-
- return value;
-}
-
-static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad,
- int phy_reg, u16 value)
-{
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
-
- if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
- clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f);
- return 0;
- }
-
- /* check parameters */
- if (phy_addr > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
- return -EINVAL;
- }
- if (phy_reg > PHY_MASK) {
- printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
- return -EINVAL;
- }
-
- /* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
- printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
- return -1;
- }
-
- writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
- ®s->smi);
- return 0;
-}
-
-/*
- * Abort any transmit and receive operations and put DMA
- * in idle state. AT and AR bits are cleared upon entering
- * in IDLE state. So poll those bits to verify operation.
- */
-static void abortdma(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- int delay;
- int maxretries = 40;
- u32 tmp;
-
- while (--maxretries) {
- writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
- udelay(100);
-
- delay = 10;
- while (--delay) {
- tmp = readl(®s->sdma_cmd);
- if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
- break;
- udelay(10);
- }
- if (delay)
- break;
- }
-
- if (!maxretries)
- printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
-}
-
-static inline u32 nibble_swapping_32_bit(u32 x)
-{
- return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
-}
-
-static inline u32 nibble_swapping_16_bit(u32 x)
-{
- return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
-}
-
-static inline u32 flip_4_bits(u32 x)
-{
- return ((x & 0x01) << 3) | ((x & 0x002) << 1)
- | ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
-}
-
-/*
- * This function will calculate the hash function of the address.
- * depends on the hash mode and hash size.
- * Inputs
- * mach - the 2 most significant bytes of the MAC address.
- * macl - the 4 least significant bytes of the MAC address.
- * Outputs
- * return the calculated entry.
- */
-static u32 hash_function(u32 mach, u32 macl)
-{
- u32 hashresult;
- u32 addrh;
- u32 addrl;
- u32 addr0;
- u32 addr1;
- u32 addr2;
- u32 addr3;
- u32 addrhswapped;
- u32 addrlswapped;
-
- addrh = nibble_swapping_16_bit(mach);
- addrl = nibble_swapping_32_bit(macl);
-
- addrhswapped = flip_4_bits(addrh & 0xf)
- + ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
- + ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
- + ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
-
- addrlswapped = flip_4_bits(addrl & 0xf)
- + ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
- + ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
- + ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
- + ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
- + ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
- + ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
- + ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
-
- addrh = addrhswapped;
- addrl = addrlswapped;
-
- addr0 = (addrl >> 2) & 0x03f;
- addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
- addr2 = (addrl >> 15) & 0x1ff;
- addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
-
- hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
- hashresult = hashresult & 0x07ff;
- return hashresult;
-}
-
-/*
- * This function will add an entry to the address table.
- * depends on the hash mode and hash size that was initialized.
- * Inputs
- * mach - the 2 most significant bytes of the MAC address.
- * macl - the 4 least significant bytes of the MAC address.
- * skip - if 1, skip this address.
- * rd - the RD field in the address table.
- * Outputs
- * address table entry is added.
- * 0 if success.
- * -ENOSPC if table full
- */
-static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
- u32 macl, u32 rd, u32 skip, int del)
-{
- struct addr_table_entry_t *entry, *start;
- u32 newhi;
- u32 newlo;
- u32 i;
-
- newlo = (((mach >> 4) & 0xf) << 15)
- | (((mach >> 0) & 0xf) << 11)
- | (((mach >> 12) & 0xf) << 7)
- | (((mach >> 8) & 0xf) << 3)
- | (((macl >> 20) & 0x1) << 31)
- | (((macl >> 16) & 0xf) << 27)
- | (((macl >> 28) & 0xf) << 23)
- | (((macl >> 24) & 0xf) << 19)
- | (skip << HTESKIP) | (rd << HTERDBIT)
- | HTEVALID;
-
- newhi = (((macl >> 4) & 0xf) << 15)
- | (((macl >> 0) & 0xf) << 11)
- | (((macl >> 12) & 0xf) << 7)
- | (((macl >> 8) & 0xf) << 3)
- | (((macl >> 21) & 0x7) << 0);
-
- /*
- * Pick the appropriate table, start scanning for free/reusable
- * entries at the index obtained by hashing the specified MAC address
- */
- start = (struct addr_table_entry_t *)(darmdfec->htpr);
- entry = start + hash_function(mach, macl);
- for (i = 0; i < HOP_NUMBER; i++) {
- if (!(entry->lo & HTEVALID)) {
- break;
- } else {
- /* if same address put in same position */
- if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
- && (entry->hi == newhi))
- break;
- }
- if (entry == start + 0x7ff)
- entry = start;
- else
- entry++;
- }
-
- if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
- (entry->hi != newhi) && del)
- return 0;
-
- if (i == HOP_NUMBER) {
- if (!del) {
- printf("ARMD100 FEC: (%s) table section is full\n",
- __func__);
- return -ENOSPC;
- } else {
- return 0;
- }
- }
-
- /*
- * Update the selected entry
- */
- if (del) {
- entry->hi = 0;
- entry->lo = 0;
- } else {
- entry->hi = newhi;
- entry->lo = newlo;
- }
-
- return 0;
-}
-
-/*
- * Create an addressTable entry from MAC address info
- * found in the specifed net_device struct
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- */
-static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
- u8 *oaddr, u8 *addr)
-{
- u32 mach;
- u32 macl;
-
- /* Delete old entry */
- if (oaddr) {
- mach = (oaddr[0] << 8) | oaddr[1];
- macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
- (oaddr[4] << 8) | oaddr[5];
- add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
- }
-
- /* Add new entry */
- mach = (addr[0] << 8) | addr[1];
- macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
- add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
-}
-
-/* Address Table Initialization */
-static void init_hashtable(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
- writel((u32)darmdfec->htpr, ®s->htpr);
-}
-
-/*
- * This detects PHY chip from address 0-31 by reading PHY status
- * registers. PHY chip can be connected at any of this address.
- */
-static int ethernet_phy_detect(struct eth_device *dev)
-{
- u32 val;
- u16 tmp, mii_status;
- u8 addr;
-
- for (addr = 0; addr < 32; addr++) {
- if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
- /* try next phy */
- continue;
-
- /* invalid MII status. More validation required here... */
- if (mii_status == 0 || mii_status == 0xffff)
- /* try next phy */
- continue;
-
- if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
- /* try next phy */
- continue;
-
- val = tmp << 16;
- if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
- /* try next phy */
- continue;
-
- val |= tmp;
-
- if ((val & 0xfffffff0) != 0)
- return addr;
- }
- return -1;
-}
-
-static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
-{
- struct rx_desc *p_rx_desc;
- int i;
-
- /* initialize the Rx descriptors ring */
- p_rx_desc = darmdfec->p_rxdesc;
- for (i = 0; i < RINGSZ; i++) {
- p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
- p_rx_desc->buf_size = PKTSIZE_ALIGN;
- p_rx_desc->byte_cnt = 0;
- p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
- if (i == (RINGSZ - 1)) {
- p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
- } else {
- p_rx_desc->nxtdesc_p = (struct rx_desc *)
- ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
- p_rx_desc = p_rx_desc->nxtdesc_p;
- }
- }
- darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
-}
-
-static int armdfec_init(struct eth_device *dev, struct bd_info *bd)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- int phy_adr;
- u32 temp;
-
- armdfec_init_rx_desc_ring(darmdfec);
-
- /* Disable interrupts */
- writel(0, ®s->im);
- writel(0, ®s->ic);
- /* Write to ICR to clear interrupts. */
- writel(0, ®s->iwc);
-
- /*
- * Abort any transmit and receive operations and put DMA
- * in idle state.
- */
- abortdma(dev);
-
- /* Initialize address hash table */
- init_hashtable(dev);
-
- /* SDMA configuration */
- writel(SDCR_BSZ8 | /* Burst size = 32 bytes */
- SDCR_RIFB | /* Rx interrupt on frame */
- SDCR_BLMT | /* Little endian transmit */
- SDCR_BLMR | /* Little endian receive */
- SDCR_RC_MAX_RETRANS, /* Max retransmit count */
- ®s->sdma_conf);
- /* Port Configuration */
- writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */
-
- /* Set extended port configuration */
- writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */
- PCXR_DSCP_EN | /* Enable DSCP in IP */
- PCXR_MFL_1536 | /* Set MTU = 1536 */
- PCXR_FLP | /* do not force link pass */
- PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
- ®s->pconf_ext);
-
- update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
-
- /* Update TX and RX queue descriptor register */
- temp = (u32)®s->txcdp[TXQ];
- writel((u32)darmdfec->p_txdesc, temp);
- temp = (u32)®s->rxfdp[RXQ];
- writel((u32)darmdfec->p_rxdesc, temp);
- temp = (u32)®s->rxcdp[RXQ];
- writel((u32)darmdfec->p_rxdesc_curr, temp);
-
- /* Enable Interrupts */
- writel(ALL_INTS, ®s->im);
-
- /* Enable Ethernet Port */
- setbits_le32(®s->pconf, PCR_EN);
-
- /* Enable RX DMA engine */
- setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
-
-#ifdef DEBUG
- eth_dump_regs(dev);
-#endif
-
-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-
-#if defined(CONFIG_PHY_BASE_ADR)
- miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
-#else
- /* Search phy address from range 0-31 */
- phy_adr = ethernet_phy_detect(dev);
- if (phy_adr < 0) {
- printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
- return -1;
- } else {
- debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
- miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
- }
-#endif
-
-#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
- /* Wait up to 5s for the link status */
- for (i = 0; i < 5; i++) {
- u16 phy_adr;
-
- miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
- /* Return if we get link up */
- if (miiphy_link(dev->name, phy_adr))
- return 0;
- udelay(1000000);
- }
-
- printf("ARMD100 FEC: No link on %s\n", dev->name);
- return -1;
-#endif
-#endif
- return 0;
-}
-
-static void armdfec_halt(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
-
- /* Stop RX DMA */
- clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
-
- /*
- * Abort any transmit and receive operations and put DMA
- * in idle state.
- */
- abortdma(dev);
-
- /* Disable interrupts */
- writel(0, ®s->im);
- writel(0, ®s->ic);
- writel(0, ®s->iwc);
-
- /* Disable Port */
- clrbits_le32(®s->pconf, PCR_EN);
-}
-
-static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct armdfec_reg *regs = darmdfec->regs;
- struct tx_desc *p_txdesc = darmdfec->p_txdesc;
- void *p = (void *)dataptr;
- int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
- u32 cmd_sts, temp;
-
- /* Copy buffer if it's misaligned */
- if ((u32)dataptr & 0x07) {
- if (datasize > PKTSIZE_ALIGN) {
- printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
- datasize);
- return -1;
- }
- memcpy(darmdfec->p_aligned_txbuf, p, datasize);
- p = darmdfec->p_aligned_txbuf;
- }
-
- p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
- p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
- p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
- p_txdesc->cmd_sts |= TX_EN_INT;
- p_txdesc->buf_ptr = p;
- p_txdesc->byte_cnt = datasize;
-
- /* Apply send command using high priority TX queue */
- temp = (u32)®s->txcdp[TXQ];
- writel((u32)p_txdesc, temp);
- writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd);
-
- /*
- * wait for packet xmit completion
- */
- cmd_sts = readl(&p_txdesc->cmd_sts);
- while (cmd_sts & BUF_OWNED_BY_DMA) {
- /* return fail if error is detected */
- if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
- (TX_ERROR | TX_LAST_DESC)) {
- printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
- return -1;
- }
- cmd_sts = readl(&p_txdesc->cmd_sts);
- if (!(retry--)) {
- printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
- __func__);
- return -1;
- }
- }
-
- return 0;
-}
-
-static int armdfec_recv(struct eth_device *dev)
-{
- struct armdfec_device *darmdfec = to_darmdfec(dev);
- struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
- u32 cmd_sts;
- u32 timeout = 0;
- u32 temp;
-
- /* wait untill rx packet available or timeout */
- do {
- if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
- timeout++;
- } else {
- debug("ARMD100 FEC: %s time out...\n", __func__);
- return -1;
- }
- } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
-
- if (p_rxdesc_curr->byte_cnt != 0) {
- debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
- "(cmd_sts= %08x)\n", __func__,
- (u32)p_rxdesc_curr->byte_cnt,
- (u32)p_rxdesc_curr->buf_ptr,
- (u32)p_rxdesc_curr->cmd_sts);
- }
-
- /*
- * In case received a packet without first/last bits on
- * OR the error summary bit is on,
- * the packets needs to be dropeed.
- */
- cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
-
- if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
- (RX_FIRST_DESC | RX_LAST_DESC)) {
- printf("ARMD100 FEC: (%s) Dropping packet spread on"
- " multiple descriptors\n", __func__);
- } else if (cmd_sts & RX_ERROR) {
- printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
- __func__);
- } else {
- /* !!! call higher layer processing */
- debug("ARMD100 FEC: (%s) Sending Received packet to"
- " upper layer (net_process_received_packet)\n", __func__);
-
- /*
- * let the upper layer handle the packet, subtract offset
- * as two dummy bytes are added in received buffer see
- * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
- */
- net_process_received_packet(
- p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET,
- (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
- }
- /*
- * free these descriptors and point next in the ring
- */
- p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
- p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
- p_rxdesc_curr->byte_cnt = 0;
-
- temp = (u32)&darmdfec->p_rxdesc_curr;
- writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
-
- return 0;
-}
-
-int armada100_fec_register(unsigned long base_addr)
-{
- struct armdfec_device *darmdfec;
- struct eth_device *dev;
-
- darmdfec = malloc(sizeof(struct armdfec_device));
- if (!darmdfec)
- goto error;
-
- memset(darmdfec, 0, sizeof(struct armdfec_device));
-
- darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
- if (!darmdfec->htpr)
- goto error1;
-
- darmdfec->p_rxdesc = memalign(PKTALIGN,
- ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
-
- if (!darmdfec->p_rxdesc)
- goto error1;
-
- darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
- if (!darmdfec->p_rxbuf)
- goto error1;
-
- darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
- if (!darmdfec->p_aligned_txbuf)
- goto error1;
-
- darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
- if (!darmdfec->p_txdesc)
- goto error1;
-
- dev = &darmdfec->dev;
- /* Assign ARMADA100 Fast Ethernet Controller Base Address */
- darmdfec->regs = (void *)base_addr;
-
- /* must be less than sizeof(dev->name) */
- strcpy(dev->name, "armd-fec0");
-
- dev->init = armdfec_init;
- dev->halt = armdfec_halt;
- dev->send = armdfec_send;
- dev->recv = armdfec_recv;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = smi_reg_read;
- mdiodev->write = smi_reg_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
- return 0;
-
-error1:
- free(darmdfec->p_aligned_txbuf);
- free(darmdfec->p_rxbuf);
- free(darmdfec->p_rxdesc);
- free(darmdfec->htpr);
-error:
- free(darmdfec);
- printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
- return -1;
-}
diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h
deleted file mode 100644
index e6f286cfd387..000000000000
--- a/drivers/net/armada100_fec.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef __ARMADA100_FEC_H__
-#define __ARMADA100_FEC_H__
-
-#define PORT_NUM 0x0
-
-/* RX & TX descriptor command */
-#define BUF_OWNED_BY_DMA (1<<31)
-
-/* RX descriptor status */
-#define RX_EN_INT (1<<23)
-#define RX_FIRST_DESC (1<<17)
-#define RX_LAST_DESC (1<<16)
-#define RX_ERROR (1<<15)
-
-/* TX descriptor command */
-#define TX_EN_INT (1<<23)
-#define TX_GEN_CRC (1<<22)
-#define TX_ZERO_PADDING (1<<18)
-#define TX_FIRST_DESC (1<<17)
-#define TX_LAST_DESC (1<<16)
-#define TX_ERROR (1<<15)
-
-/* smi register */
-#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */
-#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */
-#define SMI_OP_W (0<<26) /* Write operation */
-#define SMI_OP_R (1<<26) /* Read operation */
-
-#define HASH_ADD 0
-#define HASH_DELETE 1
-#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
-#define HOP_NUMBER 12
-
-#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
-#define PHY_WAIT_MICRO_SECONDS 10
-
-#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
-#define ETH_EXTRA_HEADER (6+6+2+4)
- /* dest+src addr+protocol id+crc */
-#define MAX_PKT_SIZE 1536
-
-
-/* Bit definitions of the SDMA Config Reg */
-#define SDCR_BSZ_OFF 12
-#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF)
-#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF)
-#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF)
-#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF)
-#define SDCR_BLMR (1<<6)
-#define SDCR_BLMT (1<<7)
-#define SDCR_RIFB (1<<9)
-#define SDCR_RC_OFF 2
-#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
-
-/* SDMA_CMD */
-#define SDMA_CMD_AT (1<<31)
-#define SDMA_CMD_TXDL (1<<24)
-#define SDMA_CMD_TXDH (1<<23)
-#define SDMA_CMD_AR (1<<15)
-#define SDMA_CMD_ERD (1<<7)
-
-
-/* Bit definitions of the Port Config Reg */
-#define PCR_HS (1<<12)
-#define PCR_EN (1<<7)
-#define PCR_PM (1<<0)
-
-/* Bit definitions of the Port Config Extend Reg */
-#define PCXR_2BSM (1<<28)
-#define PCXR_DSCP_EN (1<<21)
-#define PCXR_MFL_1518 (0<<14)
-#define PCXR_MFL_1536 (1<<14)
-#define PCXR_MFL_2048 (2<<14)
-#define PCXR_MFL_64K (3<<14)
-#define PCXR_FLP (1<<11)
-#define PCXR_PRIO_TX_OFF 3
-#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF)
-
-/*
- * * Bit definitions of the Interrupt Cause Reg
- * * and Interrupt MASK Reg is the same
- * */
-#define ICR_RXBUF (1<<0)
-#define ICR_TXBUF_H (1<<2)
-#define ICR_TXBUF_L (1<<3)
-#define ICR_TXEND_H (1<<6)
-#define ICR_TXEND_L (1<<7)
-#define ICR_RXERR (1<<8)
-#define ICR_TXERR_H (1<<10)
-#define ICR_TXERR_L (1<<11)
-#define ICR_TX_UDR (1<<13)
-#define ICR_MII_CH (1<<28)
-
-#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
- ICR_TXERR_H | ICR_TXERR_L |\
- ICR_TXEND_H | ICR_TXEND_L |\
- ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
-
-#define PHY_MASK 0x0000001f
-
-#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
- (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
-
-#define RX_BUF_OFFSET 0x2
-#define RXQ 0x0 /* RX Queue 0 */
-#define TXQ 0x1 /* TX Queue 1 */
-
-struct addr_table_entry_t {
- u32 lo;
- u32 hi;
-};
-
-/* Bit fields of a Hash Table Entry */
-enum hash_table_entry {
- HTEVALID = 1,
- HTESKIP = 2,
- HTERD = 4,
- HTERDBIT = 2
-};
-
-struct tx_desc {
- u32 cmd_sts; /* Command/status field */
- u16 reserved;
- u16 byte_cnt; /* buffer byte count */
- u8 *buf_ptr; /* pointer to buffer for this descriptor */
- struct tx_desc *nextdesc_p; /* Pointer to next descriptor */
-};
-
-struct rx_desc {
- u32 cmd_sts; /* Descriptor command status */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u16 buf_size; /* Buffer size */
- u8 *buf_ptr; /* Descriptor buffer pointer */
- struct rx_desc *nxtdesc_p; /* Next descriptor pointer */
-};
-
-/*
- * Armada100 Fast Ethernet controller Registers
- * Refer Datasheet Appendix A.22
- */
-struct armdfec_reg {
- u32 phyadr; /* PHY Address */
- u32 pad1[3];
- u32 smi; /* SMI */
- u32 pad2[0xFB];
- u32 pconf; /* Port configuration */
- u32 pad3;
- u32 pconf_ext; /* Port configuration extend */
- u32 pad4;
- u32 pcmd; /* Port Command */
- u32 pad5;
- u32 pstatus; /* Port Status */
- u32 pad6;
- u32 spar; /* Serial Parameters */
- u32 pad7;
- u32 htpr; /* Hash table pointer */
- u32 pad8;
- u32 fcsal; /* Flow control source address low */
- u32 pad9;
- u32 fcsah; /* Flow control source address high */
- u32 pad10;
- u32 sdma_conf; /* SDMA configuration */
- u32 pad11;
- u32 sdma_cmd; /* SDMA command */
- u32 pad12;
- u32 ic; /* Interrupt cause */
- u32 iwc; /* Interrupt write to clear */
- u32 im; /* Interrupt mask */
- u32 pad13;
- u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code
- Point to Priority 0 Low */
- u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */
- u32 pad14[3];
- struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor
- Pointer */
- u32 pad15[4];
- struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor
- Pointer */
- u32 pad16[0x0C];
- struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor
- Pointer */
-};
-
-struct armdfec_device {
- struct eth_device dev;
- struct armdfec_reg *regs;
- struct tx_desc *p_txdesc;
- struct rx_desc *p_rxdesc;
- struct rx_desc *p_rxdesc_curr;
- u8 *p_rxbuf;
- u8 *p_aligned_txbuf;
- u8 *htpr; /* hash pointer */
-};
-
-#endif /* __ARMADA100_FEC_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 02/10] net: Remove ax88180 driver
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
@ 2022-03-31 17:46 ` Tom Rini
2022-04-08 18:04 ` Tom Rini
2022-03-31 17:46 ` [PATCH 03/10] net: Remove cs8900 driver Tom Rini
` (8 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
This driver is not enabled by any board and not converted to DM_ETH.
Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/net/Makefile | 1 -
drivers/net/ax88180.c | 755 ------------------------------------------
drivers/net/ax88180.h | 396 ----------------------
3 files changed, 1152 deletions(-)
delete mode 100644 drivers/net/ax88180.c
delete mode 100644 drivers/net/ax88180.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b57149b33994..1d753bb7c202 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o
obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_DNET) += dnet.o
-obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c
deleted file mode 100644
index 402bcdb63ed7..000000000000
--- a/drivers/net/ax88180.c
+++ /dev/null
@@ -1,755 +0,0 @@
-/*
- * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
- *
- * This program is free software; you can distribute it and/or modify
- * it under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- * This program is distributed in the hope it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
- * USA.
- */
-
-/*
- * ========================================================================
- * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
- *
- * The AX88180 Ethernet controller is a high performance and highly
- * integrated local CPU bus Ethernet controller with embedded 40K bytes
- * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
- * embedded systems.
- * The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet
- * controller that supports both MII and RGMII interfaces and is
- * compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards.
- *
- * Please visit ASIX's web site (http://www.asix.com.tw) for more
- * details.
- *
- * Module Name : ax88180.c
- * Date : 2008-07-07
- * History
- * 09/06/2006 : New release for AX88180 US2 chip.
- * 07/07/2008 : Fix up the coding style and using inline functions
- * instead of macros
- * ========================================================================
- */
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <net.h>
-#include <malloc.h>
-#include <linux/delay.h>
-#include <linux/mii.h>
-#include "ax88180.h"
-
-/*
- * ===========================================================================
- * Local SubProgram Declaration
- * ===========================================================================
- */
-static void ax88180_rx_handler (struct eth_device *dev);
-static int ax88180_phy_initial (struct eth_device *dev);
-static void ax88180_media_config (struct eth_device *dev);
-static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev);
-static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev);
-static unsigned short ax88180_mdio_read (struct eth_device *dev,
- unsigned long regaddr);
-static void ax88180_mdio_write (struct eth_device *dev,
- unsigned long regaddr, unsigned short regdata);
-
-/*
- * ===========================================================================
- * Local SubProgram Bodies
- * ===========================================================================
- */
-static int ax88180_mdio_check_complete (struct eth_device *dev)
-{
- int us_cnt = 10000;
- unsigned short tmpval;
-
- /* MDIO read/write should not take more than 10 ms */
- while (--us_cnt) {
- tmpval = INW (dev, MDIOCTRL);
- if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0))
- break;
- }
-
- return us_cnt;
-}
-
-static unsigned short
-ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long tmpval = 0;
-
- OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
-
- if (ax88180_mdio_check_complete (dev))
- tmpval = INW (dev, MDIODP);
- else
- printf ("Failed to read PHY register!\n");
-
- return (unsigned short)(tmpval & 0xFFFF);
-}
-
-static void
-ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr,
- unsigned short regdata)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
-
- OUTW (dev, regdata, MDIODP);
-
- OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
-
- if (!ax88180_mdio_check_complete (dev))
- printf ("Failed to write PHY register!\n");
-}
-
-static int ax88180_phy_reset (struct eth_device *dev)
-{
- unsigned short delay_cnt = 500;
-
- ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE));
-
- /* Wait for the reset to complete, or time out (500 ms) */
- while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
- udelay(1000);
- if (--delay_cnt == 0) {
- printf ("Failed to reset PHY!\n");
- return -1;
- }
- }
-
- return 0;
-}
-
-static void ax88180_mac_reset (struct eth_device *dev)
-{
- unsigned long tmpval;
- unsigned char i;
-
- struct {
- unsigned short offset, value;
- } program_seq[] = {
- {
- MISC, MISC_NORMAL}, {
- RXINDICATOR, DEFAULT_RXINDICATOR}, {
- TXCMD, DEFAULT_TXCMD}, {
- TXBS, DEFAULT_TXBS}, {
- TXDES0, DEFAULT_TXDES0}, {
- TXDES1, DEFAULT_TXDES1}, {
- TXDES2, DEFAULT_TXDES2}, {
- TXDES3, DEFAULT_TXDES3}, {
- TXCFG, DEFAULT_TXCFG}, {
- MACCFG2, DEFAULT_MACCFG2}, {
- MACCFG3, DEFAULT_MACCFG3}, {
- TXLEN, DEFAULT_TXLEN}, {
- RXBTHD0, DEFAULT_RXBTHD0}, {
- RXBTHD1, DEFAULT_RXBTHD1}, {
- RXFULTHD, DEFAULT_RXFULTHD}, {
- DOGTHD0, DEFAULT_DOGTHD0}, {
- DOGTHD1, DEFAULT_DOGTHD1},};
-
- OUTW (dev, MISC_RESET_MAC, MISC);
- tmpval = INW (dev, MISC);
-
- for (i = 0; i < ARRAY_SIZE(program_seq); i++)
- OUTW (dev, program_seq[i].value, program_seq[i].offset);
-}
-
-static int ax88180_poll_tx_complete (struct eth_device *dev)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long tmpval, txbs_txdp;
- int TimeOutCnt = 10000;
-
- txbs_txdp = 1 << priv->NextTxDesc;
-
- while (TimeOutCnt--) {
-
- tmpval = INW (dev, TXBS);
-
- if ((tmpval & txbs_txdp) == 0)
- break;
-
- udelay(100);
- }
-
- if (TimeOutCnt)
- return 0;
- else
- return -TimeOutCnt;
-}
-
-static void ax88180_rx_handler (struct eth_device *dev)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long data_size;
- unsigned short rxcurt_ptr, rxbound_ptr, next_ptr;
- int i;
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
- unsigned short *rxdata = (unsigned short *)net_rx_packets[0];
-#else
- unsigned long *rxdata = (unsigned long *)net_rx_packets[0];
-#endif
- unsigned short count;
-
- rxcurt_ptr = INW (dev, RXCURT);
- rxbound_ptr = INW (dev, RXBOUND);
- next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
-
- debug ("ax88180: RX original RXBOUND=0x%04x,"
- " RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
-
- while (next_ptr != rxcurt_ptr) {
-
- OUTW (dev, RX_START_READ, RXINDICATOR);
-
- data_size = READ_RXBUF (dev) & 0xFFFF;
-
- if ((data_size == 0) || (data_size > MAX_RX_SIZE)) {
-
- OUTW (dev, RX_STOP_READ, RXINDICATOR);
-
- ax88180_mac_reset (dev);
- printf ("ax88180: Invalid Rx packet length!"
- " (len=0x%04lx)\n", data_size);
-
- debug ("ax88180: RX RXBOUND=0x%04x,"
- "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
- return;
- }
-
- rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1;
- rxbound_ptr &= RX_PAGE_NUM_MASK;
-
- /* Comput access times */
- count = (data_size + priv->PadSize) >> priv->BusWidth;
-
- for (i = 0; i < count; i++) {
- *(rxdata + i) = READ_RXBUF (dev);
- }
-
- OUTW (dev, RX_STOP_READ, RXINDICATOR);
-
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[0], data_size);
-
- OUTW (dev, rxbound_ptr, RXBOUND);
-
- rxcurt_ptr = INW (dev, RXCURT);
- rxbound_ptr = INW (dev, RXBOUND);
- next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
-
- debug ("ax88180: RX updated RXBOUND=0x%04x,"
- "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
- }
-
- return;
-}
-
-static int ax88180_phy_initial (struct eth_device *dev)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long tmp_regval;
- unsigned short phyaddr;
-
- /* Search for first avaliable PHY chipset */
-#ifdef CONFIG_PHY_ADDR
- phyaddr = CONFIG_PHY_ADDR;
-#else
- for (phyaddr = 0; phyaddr < 32; ++phyaddr)
-#endif
- {
- priv->PhyAddr = phyaddr;
- priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
- priv->PhyID1 = ax88180_mdio_read(dev, MII_PHYSID2);
-
- switch (priv->PhyID0) {
- case MARVELL_ALASKA_PHYSID0:
- debug("ax88180: Found Marvell Alaska PHY family."
- " (PHY Addr=0x%x)\n", priv->PhyAddr);
-
- switch (priv->PhyID1) {
- case MARVELL_88E1118_PHYSID1:
- ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 2);
- ax88180_mdio_write(dev, M88E1118_CR,
- M88E1118_CR_DEFAULT);
- ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 3);
- ax88180_mdio_write(dev, M88E1118_LEDCTL,
- M88E1118_LEDCTL_DEFAULT);
- ax88180_mdio_write(dev, M88E1118_LEDMIX,
- M88E1118_LEDMIX_LED050 | M88E1118_LEDMIX_LED150 | 0x15);
- ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 0);
- default: /* Default to 88E1111 Phy */
- tmp_regval = ax88180_mdio_read(dev, M88E1111_EXT_SSR);
- if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE)
- ax88180_mdio_write(dev, M88E1111_EXT_SCR,
- DEFAULT_EXT_SCR);
- }
-
- if (ax88180_phy_reset(dev) < 0)
- return 0;
- ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
-
- return 1;
-
- case CICADA_CIS8201_PHYSID0:
- debug("ax88180: Found CICADA CIS8201 PHY"
- " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
-
- ax88180_mdio_write(dev, CIS_IMR,
- (CIS_INT_ENABLE | LINK_CHANGE_INT));
-
- /* Set CIS_SMI_PRIORITY bit before force the media mode */
- tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS);
- tmp_regval &= ~CIS_SMI_PRIORITY;
- ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval);
-
- return 1;
-
- case 0xffff:
- /* No PHY at this addr */
- break;
-
- default:
- printf("ax88180: Unknown PHY chipset %#x at addr %#x\n",
- priv->PhyID0, priv->PhyAddr);
- break;
- }
- }
-
- printf("ax88180: Unknown PHY chipset!!\n");
- return 0;
-}
-
-static void ax88180_media_config (struct eth_device *dev)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned long bmcr_val, bmsr_val;
- unsigned long rxcfg_val, maccfg0_val, maccfg1_val;
- unsigned long RealMediaMode;
- int i;
-
- /* Waiting 2 seconds for PHY link stable */
- for (i = 0; i < 20000; i++) {
- bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
- if (bmsr_val & BMSR_LSTATUS) {
- break;
- }
- udelay(100);
- }
-
- bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
- debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
-
- if (bmsr_val & BMSR_LSTATUS) {
- bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
-
- if (bmcr_val & BMCR_ANENABLE) {
-
- /*
- * Waiting for Auto-negotiation completion, this may
- * take up to 5 seconds.
- */
- debug ("ax88180: Auto-negotiation is "
- "enabled. Waiting for NWay completion..\n");
- for (i = 0; i < 50000; i++) {
- bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
- if (bmsr_val & BMSR_ANEGCOMPLETE) {
- break;
- }
- udelay(100);
- }
- } else
- debug ("ax88180: Auto-negotiation is disabled.\n");
-
- debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n",
- (unsigned int)bmcr_val, (unsigned int)bmsr_val);
-
- /* Get real media mode here */
- switch (priv->PhyID0) {
- case MARVELL_ALASKA_PHYSID0:
- RealMediaMode = get_MarvellPHY_media_mode(dev);
- break;
- case CICADA_CIS8201_PHYSID0:
- RealMediaMode = get_CicadaPHY_media_mode(dev);
- break;
- default:
- RealMediaMode = MEDIA_1000FULL;
- break;
- }
-
- priv->LinkState = INS_LINK_UP;
-
- switch (RealMediaMode) {
- case MEDIA_1000FULL:
- debug ("ax88180: 1000Mbps Full-duplex mode.\n");
- rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
- maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
- maccfg1_val = GIGA_MODE_EN | RXFLOW_EN |
- FULLDUPLEX | DEFAULT_MACCFG1;
- break;
-
- case MEDIA_1000HALF:
- debug ("ax88180: 1000Mbps Half-duplex mode.\n");
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = DEFAULT_MACCFG0;
- maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1;
- break;
-
- case MEDIA_100FULL:
- debug ("ax88180: 100Mbps Full-duplex mode.\n");
- rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
- maccfg0_val = SPEED100 | TXFLOW_ENABLE
- | DEFAULT_MACCFG0;
- maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
- break;
-
- case MEDIA_100HALF:
- debug ("ax88180: 100Mbps Half-duplex mode.\n");
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = SPEED100 | DEFAULT_MACCFG0;
- maccfg1_val = DEFAULT_MACCFG1;
- break;
-
- case MEDIA_10FULL:
- debug ("ax88180: 10Mbps Full-duplex mode.\n");
- rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
- maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
- maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
- break;
-
- case MEDIA_10HALF:
- debug ("ax88180: 10Mbps Half-duplex mode.\n");
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = DEFAULT_MACCFG0;
- maccfg1_val = DEFAULT_MACCFG1;
- break;
- default:
- debug ("ax88180: Unknow media mode.\n");
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = DEFAULT_MACCFG0;
- maccfg1_val = DEFAULT_MACCFG1;
-
- priv->LinkState = INS_LINK_DOWN;
- break;
- }
-
- } else {
- rxcfg_val = DEFAULT_RXCFG;
- maccfg0_val = DEFAULT_MACCFG0;
- maccfg1_val = DEFAULT_MACCFG1;
-
- priv->LinkState = INS_LINK_DOWN;
- }
-
- OUTW (dev, rxcfg_val, RXCFG);
- OUTW (dev, maccfg0_val, MACCFG0);
- OUTW (dev, maccfg1_val, MACCFG1);
-
- return;
-}
-
-static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev)
-{
- unsigned long m88_ssr;
- unsigned long MediaMode;
-
- m88_ssr = ax88180_mdio_read (dev, M88_SSR);
- switch (m88_ssr & SSR_MEDIA_MASK) {
- case SSR_1000FULL:
- MediaMode = MEDIA_1000FULL;
- break;
- case SSR_1000HALF:
- MediaMode = MEDIA_1000HALF;
- break;
- case SSR_100FULL:
- MediaMode = MEDIA_100FULL;
- break;
- case SSR_100HALF:
- MediaMode = MEDIA_100HALF;
- break;
- case SSR_10FULL:
- MediaMode = MEDIA_10FULL;
- break;
- case SSR_10HALF:
- MediaMode = MEDIA_10HALF;
- break;
- default:
- MediaMode = MEDIA_UNKNOWN;
- break;
- }
-
- return MediaMode;
-}
-
-static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev)
-{
- unsigned long tmp_regval;
- unsigned long MediaMode;
-
- tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
- switch (tmp_regval & CIS_MEDIA_MASK) {
- case CIS_1000FULL:
- MediaMode = MEDIA_1000FULL;
- break;
- case CIS_1000HALF:
- MediaMode = MEDIA_1000HALF;
- break;
- case CIS_100FULL:
- MediaMode = MEDIA_100FULL;
- break;
- case CIS_100HALF:
- MediaMode = MEDIA_100HALF;
- break;
- case CIS_10FULL:
- MediaMode = MEDIA_10FULL;
- break;
- case CIS_10HALF:
- MediaMode = MEDIA_10HALF;
- break;
- default:
- MediaMode = MEDIA_UNKNOWN;
- break;
- }
-
- return MediaMode;
-}
-
-static void ax88180_halt (struct eth_device *dev)
-{
- /* Disable AX88180 TX/RX functions */
- OUTW (dev, WAKEMOD, CMD);
-}
-
-static int ax88180_init (struct eth_device *dev, struct bd_info * bd)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned short tmp_regval;
-
- ax88180_mac_reset (dev);
-
- /* Disable interrupt */
- OUTW (dev, CLEAR_IMR, IMR);
-
- /* Disable AX88180 TX/RX functions */
- OUTW (dev, WAKEMOD, CMD);
-
- /* Fill the MAC address */
- tmp_regval =
- dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8);
- OUTW (dev, tmp_regval, MACID0);
-
- tmp_regval =
- dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8);
- OUTW (dev, tmp_regval, MACID1);
-
- tmp_regval =
- dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
- OUTW (dev, tmp_regval, MACID2);
-
- ax88180_media_config (dev);
-
- OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
-
- /* Initial variables here */
- priv->FirstTxDesc = TXDP0;
- priv->NextTxDesc = TXDP0;
-
- /* Check if there is any invalid interrupt status and clear it. */
- OUTW (dev, INW (dev, ISR), ISR);
-
- /* Start AX88180 TX/RX functions */
- OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD);
-
- return 0;
-}
-
-/* Get a data block via Ethernet */
-static int ax88180_recv (struct eth_device *dev)
-{
- unsigned short ISR_Status;
- unsigned short tmp_regval;
-
- /* Read and check interrupt status here. */
- ISR_Status = INW (dev, ISR);
-
- while (ISR_Status) {
- /* Clear the interrupt status */
- OUTW (dev, ISR_Status, ISR);
-
- debug ("\nax88180: The interrupt status = 0x%04x\n",
- ISR_Status);
-
- if (ISR_Status & ISR_PHY) {
- /* Read ISR register once to clear PHY interrupt bit */
- tmp_regval = ax88180_mdio_read (dev, M88_ISR);
- ax88180_media_config (dev);
- }
-
- if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
- ax88180_rx_handler (dev);
- }
-
- /* Read and check interrupt status again */
- ISR_Status = INW (dev, ISR);
- }
-
- return 0;
-}
-
-/* Send a data block via Ethernet. */
-static int ax88180_send(struct eth_device *dev, void *packet, int length)
-{
- struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
- unsigned short TXDES_addr;
- unsigned short txcmd_txdp, txbs_txdp;
- unsigned short tmp_data;
- int i;
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
- volatile unsigned short *txdata = (volatile unsigned short *)packet;
-#else
- volatile unsigned long *txdata = (volatile unsigned long *)packet;
-#endif
- unsigned short count;
-
- if (priv->LinkState != INS_LINK_UP) {
- return 0;
- }
-
- priv->FirstTxDesc = priv->NextTxDesc;
- txbs_txdp = 1 << priv->FirstTxDesc;
-
- debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc);
-
- txcmd_txdp = priv->FirstTxDesc << 13;
- TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2);
-
- OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD);
-
- /* Comput access times */
- count = (length + priv->PadSize) >> priv->BusWidth;
-
- for (i = 0; i < count; i++) {
- WRITE_TXBUF (dev, *(txdata + i));
- }
-
- OUTW (dev, txcmd_txdp | length, TXCMD);
- OUTW (dev, txbs_txdp, TXBS);
- OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr);
-
- priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK;
-
- /*
- * Check the available transmit descriptor, if we had exhausted all
- * transmit descriptor ,then we have to wait for at least one free
- * descriptor
- */
- txbs_txdp = 1 << priv->NextTxDesc;
- tmp_data = INW (dev, TXBS);
-
- if (tmp_data & txbs_txdp) {
- if (ax88180_poll_tx_complete (dev) < 0) {
- ax88180_mac_reset (dev);
- priv->FirstTxDesc = TXDP0;
- priv->NextTxDesc = TXDP0;
- printf ("ax88180: Transmit time out occurred!\n");
- }
- }
-
- return 0;
-}
-
-static void ax88180_read_mac_addr (struct eth_device *dev)
-{
- unsigned short macid0_val, macid1_val, macid2_val;
- unsigned short tmp_regval;
- unsigned short i;
-
- /* Reload MAC address from EEPROM */
- OUTW (dev, RELOAD_EEPROM, PROMCTRL);
-
- /* Waiting for reload eeprom completion */
- for (i = 0; i < 500; i++) {
- tmp_regval = INW (dev, PROMCTRL);
- if ((tmp_regval & RELOAD_EEPROM) == 0)
- break;
- udelay(1000);
- }
-
- /* Get MAC addresses */
- macid0_val = INW (dev, MACID0);
- macid1_val = INW (dev, MACID1);
- macid2_val = INW (dev, MACID2);
-
- if (((macid0_val | macid1_val | macid2_val) != 0) &&
- ((macid0_val & 0x01) == 0)) {
- dev->enetaddr[0] = (unsigned char)macid0_val;
- dev->enetaddr[1] = (unsigned char)(macid0_val >> 8);
- dev->enetaddr[2] = (unsigned char)macid1_val;
- dev->enetaddr[3] = (unsigned char)(macid1_val >> 8);
- dev->enetaddr[4] = (unsigned char)macid2_val;
- dev->enetaddr[5] = (unsigned char)(macid2_val >> 8);
- }
-}
-
-/* Exported SubProgram Bodies */
-int ax88180_initialize (struct bd_info * bis)
-{
- struct eth_device *dev;
- struct ax88180_private *priv;
-
- dev = (struct eth_device *)malloc (sizeof *dev);
-
- if (NULL == dev)
- return 0;
-
- memset (dev, 0, sizeof *dev);
-
- priv = (struct ax88180_private *)malloc (sizeof (*priv));
-
- if (NULL == priv)
- return 0;
-
- memset (priv, 0, sizeof *priv);
-
- strcpy(dev->name, "ax88180");
- dev->iobase = AX88180_BASE;
- dev->priv = priv;
- dev->init = ax88180_init;
- dev->halt = ax88180_halt;
- dev->send = ax88180_send;
- dev->recv = ax88180_recv;
-
- priv->BusWidth = BUS_WIDTH_32;
- priv->PadSize = 3;
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
- OUTW (dev, (START_BASE >> 8), BASE);
- OUTW (dev, DECODE_EN, DECODE);
-
- priv->BusWidth = BUS_WIDTH_16;
- priv->PadSize = 1;
-#endif
-
- ax88180_mac_reset (dev);
-
- /* Disable interrupt */
- OUTW (dev, CLEAR_IMR, IMR);
-
- /* Disable AX88180 TX/RX functions */
- OUTW (dev, WAKEMOD, CMD);
-
- ax88180_read_mac_addr (dev);
-
- eth_register (dev);
-
- return ax88180_phy_initial (dev);
-
-}
diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h
deleted file mode 100644
index daf18e015709..000000000000
--- a/drivers/net/ax88180.h
+++ /dev/null
@@ -1,396 +0,0 @@
-/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
-/*
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- */
-
-#ifndef _AX88180_H_
-#define _AX88180_H_
-
-#include <asm/io.h>
-#include <asm/types.h>
-#include <config.h>
-
-typedef enum _ax88180_link_state {
- INS_LINK_DOWN,
- INS_LINK_UP,
- INS_LINK_UNKNOWN
-} ax88180_link_state;
-
-struct ax88180_private {
- unsigned char BusWidth;
- unsigned char PadSize;
- unsigned short PhyAddr;
- unsigned short PhyID0;
- unsigned short PhyID1;
- unsigned short FirstTxDesc;
- unsigned short NextTxDesc;
- ax88180_link_state LinkState;
-};
-
-#define BUS_WIDTH_16 1
-#define BUS_WIDTH_32 2
-
-#define ENABLE_JUMBO 1
-#define DISABLE_JUMBO 0
-
-#define ENABLE_BURST 1
-#define DISABLE_BURST 0
-
-#define NORMAL_RX_MODE 0
-#define RX_LOOPBACK_MODE 1
-#define RX_INIFINIT_LOOP_MODE 2
-#define TX_INIFINIT_LOOP_MODE 3
-
-#define DEFAULT_ETH_MTU 1500
-
-/* Jumbo packet size 4086 bytes included 4 bytes CRC*/
-#define MAX_JUMBO_MTU 4072
-
-/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
-#define MAX_TX_JUMBO_SIZE 4086
-
-/* Max Rx Jumbo size is 15K Bytes */
-#define MAX_RX_SIZE 0x3C00
-
-#define MARVELL_ALASKA_PHYSID0 0x141
-#define MARVELL_88E1118_PHYSID1 0xE40
-
-#define CICADA_CIS8201_PHYSID0 0x000F
-
-#define MEDIA_AUTO 0
-#define MEDIA_1000FULL 1
-#define MEDIA_1000HALF 2
-#define MEDIA_100FULL 3
-#define MEDIA_100HALF 4
-#define MEDIA_10FULL 5
-#define MEDIA_10HALF 6
-#define MEDIA_UNKNOWN 7
-
-#define AUTO_MEDIA 0
-#define FORCE_MEDIA 1
-
-#define TXDP_MASK 3
-#define TXDP0 0
-#define TXDP1 1
-#define TXDP2 2
-#define TXDP3 3
-
-#define CMD_MAP_SIZE 0x100
-
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
- #define AX88180_MEMORY_SIZE 0x00004000
- #define START_BASE 0x1000
-
- #define RX_BUF_SIZE 0x1000
- #define TX_BUF_SIZE 0x0F00
-
- #define TX_BASE START_BASE
- #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
- #define RX_BASE (CMD_BASE + CMD_MAP_SIZE)
-#else
- #define AX88180_MEMORY_SIZE 0x00010000
-
- #define RX_BUF_SIZE 0x8000
- #define TX_BUF_SIZE 0x7C00
-
- #define RX_BASE 0x0000
- #define TX_BASE (RX_BASE + RX_BUF_SIZE)
- #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
-#endif
-
-/* AX88180 Memory Mapping Definition */
-#define RXBUFFER_START RX_BASE
- #define RX_PACKET_LEN_OFFSET 0
- #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
-#define TXBUFFER_START TX_BASE
-
-/* AX88180 MAC Register Definition */
-#define DECODE (0)
- #define DECODE_EN 0x00000001
-#define BASE (6)
-#define CMD (CMD_BASE + 0x0000)
- #define WAKEMOD 0x00000001
- #define TXEN 0x00000100
- #define RXEN 0x00000200
- #define DEFAULT_CMD WAKEMOD
-#define IMR (CMD_BASE + 0x0004)
- #define IMR_RXBUFFOVR 0x00000001
- #define IMR_WATCHDOG 0x00000002
- #define IMR_TX 0x00000008
- #define IMR_RX 0x00000010
- #define IMR_PHY 0x00000020
- #define CLEAR_IMR 0x00000000
- #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\
- IMR_RXBUFFOVR | IMR_WATCHDOG)
-#define ISR (CMD_BASE + 0x0008)
- #define ISR_RXBUFFOVR 0x00000001
- #define ISR_WATCHDOG 0x00000002
- #define ISR_TX 0x00000008
- #define ISR_RX 0x00000010
- #define ISR_PHY 0x00000020
-#define TXCFG (CMD_BASE + 0x0010)
- #define AUTOPAD_CRC 0x00000050
- #define DEFAULT_TXCFG AUTOPAD_CRC
-#define TXCMD (CMD_BASE + 0x0014)
- #define TXCMD_TXDP_MASK 0x00006000
- #define TXCMD_TXDP0 0x00000000
- #define TXCMD_TXDP1 0x00002000
- #define TXCMD_TXDP2 0x00004000
- #define TXCMD_TXDP3 0x00006000
- #define TX_START_WRITE 0x00008000
- #define TX_STOP_WRITE 0x00000000
- #define DEFAULT_TXCMD 0x00000000
-#define TXBS (CMD_BASE + 0x0018)
- #define TXDP0_USED 0x00000001
- #define TXDP1_USED 0x00000002
- #define TXDP2_USED 0x00000004
- #define TXDP3_USED 0x00000008
- #define DEFAULT_TXBS 0x00000000
-#define TXDES0 (CMD_BASE + 0x0020)
- #define TXDPx_ENABLE 0x00008000
- #define TXDPx_LEN_MASK 0x00001FFF
- #define DEFAULT_TXDES0 0x00000000
-#define TXDES1 (CMD_BASE + 0x0024)
- #define TXDPx_ENABLE 0x00008000
- #define TXDPx_LEN_MASK 0x00001FFF
- #define DEFAULT_TXDES1 0x00000000
-#define TXDES2 (CMD_BASE + 0x0028)
- #define TXDPx_ENABLE 0x00008000
- #define TXDPx_LEN_MASK 0x00001FFF
- #define DEFAULT_TXDES2 0x00000000
-#define TXDES3 (CMD_BASE + 0x002C)
- #define TXDPx_ENABLE 0x00008000
- #define TXDPx_LEN_MASK 0x00001FFF
- #define DEFAULT_TXDES3 0x00000000
-#define RXCFG (CMD_BASE + 0x0030)
- #define RXBUFF_PROTECT 0x00000001
- #define RXTCPCRC_CHECK 0x00000010
- #define RXFLOW_ENABLE 0x00000100
- #define DEFAULT_RXCFG RXBUFF_PROTECT
-#define RXCURT (CMD_BASE + 0x0034)
- #define DEFAULT_RXCURT 0x00000000
-#define RXBOUND (CMD_BASE + 0x0038)
- #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */
-#define MACCFG0 (CMD_BASE + 0x0040)
- #define MACCFG0_BIT3_0 0x00000007
- #define IPGT_VAL 0x00000150
- #define TXFLOW_ENABLE 0x00001000
- #define SPEED100 0x00008000
- #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0)
-#define MACCFG1 (CMD_BASE + 0x0044)
- #define RGMII_EN 0x00000002
- #define RXFLOW_EN 0x00000020
- #define FULLDUPLEX 0x00000040
- #define MAX_JUMBO_LEN 0x00000780
- #define RXJUMBO_EN 0x00000800
- #define GIGA_MODE_EN 0x00001000
- #define RXCRC_CHECK 0x00002000
- #define RXPAUSE_DA_CHECK 0x00004000
-
- #define JUMBO_LEN_4K 0x00000200
- #define JUMBO_LEN_15K 0x00000780
- #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \
- RGMII_EN)
- #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK)
-#define MACCFG2 (CMD_BASE + 0x0048)
- #define MACCFG2_BIT15_8 0x00000100
- #define JAM_LIMIT_MASK 0x000000FC
- #define DEFAULT_JAM_LIMIT 0x00000064
- #define DEFAULT_MACCFG2 MACCFG2_BIT15_8
-#define MACCFG3 (CMD_BASE + 0x004C)
- #define IPGR2_VAL 0x0000000E
- #define IPGR1_VAL 0x00000600
- #define NOABORT 0x00008000
- #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL)
-#define TXPAUT (CMD_BASE + 0x0054)
- #define DEFAULT_TXPAUT 0x001FE000
-#define RXBTHD0 (CMD_BASE + 0x0058)
- #define DEFAULT_RXBTHD0 0x00000300
-#define RXBTHD1 (CMD_BASE + 0x005C)
- #define DEFAULT_RXBTHD1 0x00000600
-#define RXFULTHD (CMD_BASE + 0x0060)
- #define DEFAULT_RXFULTHD 0x00000100
-#define MISC (CMD_BASE + 0x0068)
- /* Normal operation mode */
- #define MISC_NORMAL 0x00000003
- /* Clear bit 0 to reset MAC */
- #define MISC_RESET_MAC 0x00000002
- /* Clear bit 1 to reset PHY */
- #define MISC_RESET_PHY 0x00000001
- /* Clear bit 0 and 1 to reset MAC and PHY */
- #define MISC_RESET_MAC_PHY 0x00000000
- #define DEFAULT_MISC MISC_NORMAL
-#define MACID0 (CMD_BASE + 0x0070)
-#define MACID1 (CMD_BASE + 0x0074)
-#define MACID2 (CMD_BASE + 0x0078)
-#define TXLEN (CMD_BASE + 0x007C)
- #define DEFAULT_TXLEN 0x000005FC
-#define RXFILTER (CMD_BASE + 0x0080)
- #define RX_RXANY 0x00000001
- #define RX_MULTICAST 0x00000002
- #define RX_UNICAST 0x00000004
- #define RX_BROADCAST 0x00000008
- #define RX_MULTI_HASH 0x00000010
- #define DISABLE_RXFILTER 0x00000000
- #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST)
-#define MDIOCTRL (CMD_BASE + 0x0084)
- #define PHY_ADDR_MASK 0x0000001F
- #define REG_ADDR_MASK 0x00001F00
- #define READ_PHY 0x00004000
- #define WRITE_PHY 0x00008000
-#define MDIODP (CMD_BASE + 0x0088)
-#define GPIOCTRL (CMD_BASE + 0x008C)
-#define RXINDICATOR (CMD_BASE + 0x0090)
- #define RX_START_READ 0x00000001
- #define RX_STOP_READ 0x00000000
- #define DEFAULT_RXINDICATOR RX_STOP_READ
-#define TXST (CMD_BASE + 0x0094)
-#define MDCCLKPAT (CMD_BASE + 0x00A0)
-#define RXIPCRCCNT (CMD_BASE + 0x00A4)
-#define RXCRCCNT (CMD_BASE + 0x00A8)
-#define TXFAILCNT (CMD_BASE + 0x00AC)
-#define PROMDP (CMD_BASE + 0x00B0)
-#define PROMCTRL (CMD_BASE + 0x00B4)
- #define RELOAD_EEPROM 0x00000200
-#define MAXRXLEN (CMD_BASE + 0x00B8)
-#define HASHTAB0 (CMD_BASE + 0x00C0)
-#define HASHTAB1 (CMD_BASE + 0x00C4)
-#define HASHTAB2 (CMD_BASE + 0x00C8)
-#define HASHTAB3 (CMD_BASE + 0x00CC)
-#define DOGTHD0 (CMD_BASE + 0x00E0)
- #define DEFAULT_DOGTHD0 0x0000FFFF
-#define DOGTHD1 (CMD_BASE + 0x00E4)
- #define START_WATCHDOG_TIMER 0x00008000
- #define DEFAULT_DOGTHD1 0x00000FFF
-#define SOFTRST (CMD_BASE + 0x00EC)
- #define SOFTRST_NORMAL 0x00000003
- #define SOFTRST_RESET_MAC 0x00000002
-
-/* Marvell 88E1111 Gigabit PHY Register Definition */
-#define M88_SSR 0x0011
- #define SSR_SPEED_MASK 0xC000
- #define SSR_SPEED_1000 0x8000
- #define SSR_SPEED_100 0x4000
- #define SSR_SPEED_10 0x0000
- #define SSR_DUPLEX 0x2000
- #define SSR_MEDIA_RESOLVED_OK 0x0800
-
- #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX)
- #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX)
- #define SSR_1000HALF SSR_SPEED_1000
- #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX)
- #define SSR_100HALF SSR_SPEED_100
- #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX)
- #define SSR_10HALF SSR_SPEED_10
-#define M88_IER 0x0012
- #define LINK_CHANGE_INT 0x0400
-#define M88_ISR 0x0013
- #define LINK_CHANGE_STATUS 0x0400
-#define M88E1111_EXT_SCR 0x0014
- #define RGMII_RXCLK_DELAY 0x0080
- #define RGMII_TXCLK_DELAY 0x0002
- #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
-#define M88E1111_EXT_SSR 0x001B
- #define HWCFG_MODE_MASK 0x000F
- #define RGMII_COPPER_MODE 0x000B
-
-/* Marvell 88E1118 Gigabit PHY Register Definition */
-#define M88E1118_CR 0x14
- #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
- #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
- #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
- M88E1118_CR_RGMII_RXCLK_DELAY)
-#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
- #define M88E1118_LEDCTL_LED2INT 0x200
- #define M88E1118_LEDCTL_LED2BLNK 0x400
- #define M88E1118_LEDCTL_LED0DUALMODE1 0xc
- #define M88E1118_LEDCTL_LED0DUALMODE2 0xd
- #define M88E1118_LEDCTL_LED0DUALMODE3 0xe
- #define M88E1118_LEDCTL_LED0DUALMODE4 0xf
- #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
- M88E1118_LEDCTL_LED0DUALMODE4)
-
-#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
- #define M88E1118_LEDMIX_LED050 0x4
- #define M88E1118_LEDMIX_LED150 0x8
-
-#define M88E1118_PAGE_SEL 0x16 /* Reg page select */
-
-/* CICADA CIS8201 Gigabit PHY Register Definition */
-#define CIS_IMR 0x0019
- #define CIS_INT_ENABLE 0x8000
- #define CIS_LINK_CHANGE_INT 0x2000
-#define CIS_ISR 0x001A
- #define CIS_INT_PENDING 0x8000
- #define CIS_LINK_CHANGE_STATUS 0x2000
-#define CIS_AUX_CTRL_STATUS 0x001C
- #define CIS_AUTONEG_COMPLETE 0x8000
- #define CIS_SPEED_MASK 0x0018
- #define CIS_SPEED_1000 0x0010
- #define CIS_SPEED_100 0x0008
- #define CIS_SPEED_10 0x0000
- #define CIS_DUPLEX 0x0020
-
- #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX)
- #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX)
- #define CIS_1000HALF CIS_SPEED_1000
- #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX)
- #define CIS_100HALF CIS_SPEED_100
- #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX)
- #define CIS_10HALF CIS_SPEED_10
- #define CIS_SMI_PRIORITY 0x0004
-
-static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
-{
- return le16_to_cpu(readw(addr + (void *)dev->iobase));
-}
-
-/*
- Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
-*/
-#if defined (CONFIG_DRIVER_AX88180_16BIT)
-static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
-{
- writew(cpu_to_le16(command), addr + (void *)dev->iobase);
-}
-
-static inline unsigned short READ_RXBUF (struct eth_device *dev)
-{
- return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase));
-}
-
-static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
-{
- writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase);
-}
-#else
-static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
-{
- writel(cpu_to_le32(command), addr + (void *)dev->iobase);
-}
-
-static inline unsigned long READ_RXBUF (struct eth_device *dev)
-{
- return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase));
-}
-
-static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
-{
- writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase);
-}
-#endif
-
-#endif /* _AX88180_H_ */
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 03/10] net: Remove cs8900 driver
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
2022-03-31 17:46 ` [PATCH 02/10] net: Remove ax88180 driver Tom Rini
@ 2022-03-31 17:46 ` Tom Rini
2022-04-08 18:04 ` Tom Rini
2022-03-31 17:46 ` [PATCH 04/10] net: Remove dnet driver Tom Rini
` (7 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
This driver is not enabled by any board and not converted to DM_ETH.
Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/net/Makefile | 1 -
drivers/net/cs8900.c | 320 -------------------------------------------
drivers/net/cs8900.h | 248 ---------------------------------
3 files changed, 569 deletions(-)
delete mode 100644 drivers/net/cs8900.c
delete mode 100644 drivers/net/cs8900.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 1d753bb7c202..967f82c5157e 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
obj-$(CONFIG_BNXT_ETH) += bnxt/
obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o
-obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_DNET) += dnet.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c
deleted file mode 100644
index 9440a91882f9..000000000000
--- a/drivers/net/cs8900.c
+++ /dev/null
@@ -1,320 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic CS8900A Ethernet
- *
- * (C) 2009 Ben Warren , biggerbadderben@gmail.com
- * Converted to use CONFIG_NET_MULTI API
- *
- * (C) 2003 Wolfgang Denk, wd@denx.de
- * Extension to synchronize ethaddr environment variable
- * against value in EEPROM
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
- *
- * This program is loaded into SRAM in bootstrap mode, where it waits
- * for commands on UART1 to read and write memory, jump to code etc.
- * A design goal for this program is to be entirely independent of the
- * target board. Anything with a CL-PS7111 or EP7211 should be able to run
- * this code in bootstrap mode. All the board specifics can be handled on
- * the host.
- */
-
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <asm/io.h>
-#include <net.h>
-#include <malloc.h>
-#include <linux/delay.h>
-#include "cs8900.h"
-
-#undef DEBUG
-
-/* packet page register access functions */
-
-#ifdef CONFIG_CS8900_BUS32
-
-#define REG_WRITE(v, a) writel((v),(a))
-#define REG_READ(a) readl((a))
-
-/* we don't need 16 bit initialisation on 32 bit bus */
-#define get_reg_init_bus(r,d) get_reg((r),(d))
-
-#else
-
-#define REG_WRITE(v, a) writew((v),(a))
-#define REG_READ(a) readw((a))
-
-static u16 get_reg_init_bus(struct eth_device *dev, int regno)
-{
- /* force 16 bit busmode */
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
- uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
-
- readb(iob);
- readb(iob + 1);
- readb(iob);
- readb(iob + 1);
- readb(iob);
-
- REG_WRITE(regno, &priv->regs->pptr);
- return REG_READ(&priv->regs->pdata);
-}
-#endif
-
-static u16 get_reg(struct eth_device *dev, int regno)
-{
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
- REG_WRITE(regno, &priv->regs->pptr);
- return REG_READ(&priv->regs->pdata);
-}
-
-
-static void put_reg(struct eth_device *dev, int regno, u16 val)
-{
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
- REG_WRITE(regno, &priv->regs->pptr);
- REG_WRITE(val, &priv->regs->pdata);
-}
-
-static void cs8900_reset(struct eth_device *dev)
-{
- int tmo;
- u16 us;
-
- /* reset NIC */
- put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
-
- /* wait for 200ms */
- udelay(200000);
- /* Wait until the chip is reset */
-
- tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
- while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
- PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
- /*NOP*/;
-}
-
-static void cs8900_reginit(struct eth_device *dev)
-{
- /* receive only error free packets addressed to this card */
- put_reg(dev, PP_RxCTL,
- PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
- /* do not generate any interrupts on receive operations */
- put_reg(dev, PP_RxCFG, 0);
- /* do not generate any interrupts on transmit operations */
- put_reg(dev, PP_TxCFG, 0);
- /* do not generate any interrupts on buffer operations */
- put_reg(dev, PP_BufCFG, 0);
- /* enable transmitter/receiver mode */
- put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
-}
-
-void cs8900_get_enetaddr(struct eth_device *dev)
-{
- int i;
-
- /* verify chip id */
- if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
- return;
- cs8900_reset(dev);
- if ((get_reg(dev, PP_SelfSTAT) &
- (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
- (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
-
- /* Load the MAC from EEPROM */
- for (i = 0; i < 3; i++) {
- u32 Addr;
-
- Addr = get_reg(dev, PP_IA + i * 2);
- dev->enetaddr[i * 2] = Addr & 0xFF;
- dev->enetaddr[i * 2 + 1] = Addr >> 8;
- }
- }
-}
-
-void cs8900_halt(struct eth_device *dev)
-{
- /* disable transmitter/receiver mode */
- put_reg(dev, PP_LineCTL, 0);
-
- /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
- get_reg_init_bus(dev, PP_ChipID);
-}
-
-static int cs8900_init(struct eth_device *dev, struct bd_info * bd)
-{
- uchar *enetaddr = dev->enetaddr;
- u16 id;
-
- /* verify chip id */
- id = get_reg_init_bus(dev, PP_ChipID);
- if (id != 0x630e) {
- printf ("CS8900 Ethernet chip not found: "
- "ID=0x%04x instead 0x%04x\n", id, 0x630e);
- return 1;
- }
-
- cs8900_reset (dev);
- /* set the ethernet address */
- put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
- put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
- put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
-
- cs8900_reginit(dev);
- return 0;
-}
-
-/* Get a data block via Ethernet */
-static int cs8900_recv(struct eth_device *dev)
-{
- int i;
- u16 rxlen;
- u16 *addr;
- u16 status;
-
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
-
- status = get_reg(dev, PP_RER);
-
- if ((status & PP_RER_RxOK) == 0)
- return 0;
-
- status = REG_READ(&priv->regs->rtdata);
- rxlen = REG_READ(&priv->regs->rtdata);
-
- if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
- debug("packet too big!\n");
- for (addr = (u16 *)net_rx_packets[0], i = rxlen >> 1; i > 0; i--)
- *addr++ = REG_READ(&priv->regs->rtdata);
- if (rxlen & 1)
- *addr++ = REG_READ(&priv->regs->rtdata);
-
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[0], rxlen);
- return rxlen;
-}
-
-/* Send a data block via Ethernet. */
-static int cs8900_send(struct eth_device *dev, void *packet, int length)
-{
- volatile u16 *addr;
- int tmo;
- u16 s;
- struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
-
-retry:
- /* initiate a transmit sequence */
- REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
- REG_WRITE(length, &priv->regs->txlen);
-
- /* Test to see if the chip has allocated memory for the packet */
- if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
- /* Oops... this should not happen! */
- debug("cs: unable to send packet; retrying...\n");
- for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
- get_timer(0) < tmo;)
- /*NOP*/;
- cs8900_reset(dev);
- cs8900_reginit(dev);
- goto retry;
- }
-
- /* Write the contents of the packet */
- /* assume even number of bytes */
- for (addr = packet; length > 0; length -= 2)
- REG_WRITE(*addr++, &priv->regs->rtdata);
-
- /* wait for transfer to succeed */
- tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
- while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
- if (get_timer(0) >= tmo)
- break;
- }
-
- /* nothing */ ;
- if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
- debug("\ntransmission error %#x\n", s);
- }
-
- return 0;
-}
-
-static void cs8900_e2prom_ready(struct eth_device *dev)
-{
- while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
- ;
-}
-
-/***********************************************************/
-/* read a 16-bit word out of the EEPROM */
-/***********************************************************/
-
-int cs8900_e2prom_read(struct eth_device *dev,
- u8 addr, u16 *value)
-{
- cs8900_e2prom_ready(dev);
- put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
- cs8900_e2prom_ready(dev);
- *value = get_reg(dev, PP_EEData);
-
- return 0;
-}
-
-
-/***********************************************************/
-/* write a 16-bit word into the EEPROM */
-/***********************************************************/
-
-int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
-{
- cs8900_e2prom_ready(dev);
- put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
- cs8900_e2prom_ready(dev);
- put_reg(dev, PP_EEData, value);
- put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
- cs8900_e2prom_ready(dev);
- put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
- cs8900_e2prom_ready(dev);
-
- return 0;
-}
-
-int cs8900_initialize(u8 dev_num, int base_addr)
-{
- struct eth_device *dev;
- struct cs8900_priv *priv;
-
- dev = malloc(sizeof(*dev));
- if (!dev) {
- return 0;
- }
- memset(dev, 0, sizeof(*dev));
-
- priv = malloc(sizeof(*priv));
- if (!priv) {
- free(dev);
- return 0;
- }
- memset(priv, 0, sizeof(*priv));
- priv->regs = (struct cs8900_regs *)base_addr;
-
- dev->iobase = base_addr;
- dev->priv = priv;
- dev->init = cs8900_init;
- dev->halt = cs8900_halt;
- dev->send = cs8900_send;
- dev->recv = cs8900_recv;
-
- /* Load MAC address from EEPROM */
- cs8900_get_enetaddr(dev);
-
- sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
-
- eth_register(dev);
- return 0;
-}
diff --git a/drivers/net/cs8900.h b/drivers/net/cs8900.h
deleted file mode 100644
index 1a566ff7b2ec..000000000000
--- a/drivers/net/cs8900.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef CS8900_H
-#define CS8900_H
-/*
- * Cirrus Logic CS8900A Ethernet
- *
- * (C) 2009 Ben Warren , biggerbadderben@gmail.com
- * Converted to use CONFIG_NET_MULTI API
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
- *
- * This program is loaded into SRAM in bootstrap mode, where it waits
- * for commands on UART1 to read and write memory, jump to code etc.
- * A design goal for this program is to be entirely independent of the
- * target board. Anything with a CL-PS7111 or EP7211 should be able to run
- * this code in bootstrap mode. All the board specifics can be handled on
- * the host.
- */
-
-#include <asm/types.h>
-#include <config.h>
-
-#define CS8900_DRIVERNAME "CS8900"
-/* although the registers are 16 bit, they are 32-bit aligned on the
- EDB7111. so we have to read them as 32-bit registers and ignore the
- upper 16-bits. i'm not sure if this holds for the EDB7211. */
-
-#ifdef CONFIG_CS8900_BUS16
- /* 16 bit aligned registers, 16 bit wide */
- #define CS8900_REG u16
-#elif defined(CONFIG_CS8900_BUS32)
- /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
- #define CS8900_REG u32
-#else
- #error unknown bussize ...
-#endif
-
-struct cs8900_regs {
- CS8900_REG rtdata;
- CS8900_REG pad0;
- CS8900_REG txcmd;
- CS8900_REG txlen;
- CS8900_REG isq;
- CS8900_REG pptr;
- CS8900_REG pdata;
-};
-
-struct cs8900_priv {
- struct cs8900_regs *regs;
-};
-
-#define ISQ_RxEvent 0x04
-#define ISQ_TxEvent 0x08
-#define ISQ_BufEvent 0x0C
-#define ISQ_RxMissEvent 0x10
-#define ISQ_TxColEvent 0x12
-#define ISQ_EventMask 0x3F
-
-/* packet page register offsets */
-
-/* bus interface registers */
-#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */
-#define PP_ChipRev 0x0002 /* Chip revision, model codes */
-
-#define PP_IntReg 0x0022 /* Interrupt configuration */
-#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */
-#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */
-#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */
-#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */
-
-/* status and control registers */
-
-#define PP_RxCFG 0x0102 /* Receiver configuration */
-#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */
-#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */
-#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */
-#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */
-#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */
-#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */
-#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */
-#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */
-#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */
-
-#define PP_RxCTL 0x0104 /* Receiver control */
-#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */
-#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */
-#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */
-#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */
-#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */
-#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */
-#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */
-#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */
-#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */
-
-#define PP_TxCFG 0x0106 /* Transmit configuration */
-#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */
-#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */
-#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */
-#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */
-#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */
-#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */
-#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */
-
-#define PP_TxCmd 0x0108 /* Transmit command status */
-#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */
-#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */
-#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */
-#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */
-#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */
-#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */
-#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */
-#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */
-
-#define PP_BufCFG 0x010A /* Buffer configuration */
-#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */
-#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */
-#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */
-#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */
-#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */
-#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */
-#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */
-#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */
-#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */
-
-#define PP_LineCTL 0x0112 /* Line control */
-#define PP_LineCTL_Rx 0x0040 /* Enable receiver */
-#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */
-#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */
-#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */
-#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */
-#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */
-#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */
-#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */
-
-#define PP_SelfCTL 0x0114 /* Chip self control */
-#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */
-#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */
-#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */
-#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */
-#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */
-#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */
-#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */
-#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */
-
-#define PP_BusCTL 0x0116 /* Bus control */
-#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */
-#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */
-#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */
-#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */
-#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */
-#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */
-#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */
-#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */
-
-#define PP_TestCTL 0x0118 /* Test control */
-#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */
-#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */
-#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */
-#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */
-#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */
-
-#define PP_ISQ 0x0120 /* Interrupt Status Queue */
-
-#define PP_RER 0x0124 /* Receive event */
-#define PP_RER_IAHash 0x0040 /* Frame hash match */
-#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */
-#define PP_RER_RxOK 0x0100 /* Frame received with no errors */
-#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */
-#define PP_RER_IA 0x0400 /* Frame address matched IA */
-#define PP_RER_Broadcast 0x0800 /* Broadcast frame */
-#define PP_RER_CRC 0x1000 /* Frame had CRC error */
-#define PP_RER_RUNT 0x2000 /* Runt frame */
-#define PP_RER_EXTRA 0x4000 /* Frame was too long */
-
-#define PP_TER 0x0128 /* Transmit event */
-#define PP_TER_CRS 0x0040 /* Carrier lost */
-#define PP_TER_SQE 0x0080 /* Signal Quality Error */
-#define PP_TER_TxOK 0x0100 /* Packet sent without error */
-#define PP_TER_Late 0x0200 /* Out of window */
-#define PP_TER_Jabber 0x0400 /* Stuck transmit? */
-#define PP_TER_NumCollisions 0x7800 /* Number of collisions */
-#define PP_TER_16Collisions 0x8000 /* > 16 collisions */
-
-#define PP_BER 0x012C /* Buffer event */
-#define PP_BER_SWint 0x0040 /* Software interrupt */
-#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */
-#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */
-#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */
-#define PP_BER_RxMiss 0x0400 /* Received frame missed */
-#define PP_BER_Rx128 0x0800 /* 128 bytes received */
-#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */
-
-#define PP_RxMiss 0x0130 /* Receiver miss counter */
-
-#define PP_TxCol 0x0132 /* Transmit collision counter */
-
-#define PP_LineSTAT 0x0134 /* Line status */
-#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */
-#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */
-#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */
-#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */
-#define PP_LineSTAT_CRS 0x4000 /* Frame being received */
-
-#define PP_SelfSTAT 0x0136 /* Chip self status */
-#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */
-#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */
-#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */
-#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */
-#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */
-#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */
-#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */
-
-#define PP_BusSTAT 0x0138 /* Bus status */
-#define PP_BusSTAT_TxBid 0x0080 /* Tx error */
-#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */
-
-#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */
-
-/* initiate transmit registers */
-
-#define PP_TxCommand 0x0144 /* Tx Command */
-#define PP_TxLength 0x0146 /* Tx Length */
-
-
-/* address filter registers */
-
-#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */
-#define PP_IA 0x0158 /* Individual address (MAC) */
-
-/* EEPROM Kram */
-#define SI_BUSY 0x0100
-#define PP_EECMD 0x0040 /* NVR Interface Command register */
-#define PP_EEData 0x0042 /* NVR Interface Data Register */
-#define EEPROM_WRITE_EN 0x00F0
-#define EEPROM_WRITE_DIS 0x0000
-#define EEPROM_WRITE_CMD 0x0100
-#define EEPROM_READ_CMD 0x0200
-#define EEPROM_ERASE_CMD 0x0300
-
-/* Exported functions */
-int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *);
-int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort);
-
-#endif /* CS8900_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 04/10] net: Remove dnet driver
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
2022-03-31 17:46 ` [PATCH 02/10] net: Remove ax88180 driver Tom Rini
2022-03-31 17:46 ` [PATCH 03/10] net: Remove cs8900 driver Tom Rini
@ 2022-03-31 17:46 ` Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 05/10] net: Remove ftmac110 driver Tom Rini
` (6 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
This driver is not enabled by any board and not converted to DM_ETH.
Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/net/Makefile | 1 -
drivers/net/dnet.c | 395 -------------------------------------------
drivers/net/dnet.h | 166 ------------------
3 files changed, 562 deletions(-)
delete mode 100644 drivers/net/dnet.c
delete mode 100644 drivers/net/dnet.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 967f82c5157e..1fcd1b2d0b8d 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_BNXT_ETH) += bnxt/
obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o
obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
-obj-$(CONFIG_DNET) += dnet.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c
deleted file mode 100644
index fbcf15f26801..000000000000
--- a/drivers/net/dnet.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * Dave Ethernet Controller driver
- *
- * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <log.h>
-#include <linux/delay.h>
-
-#ifndef CONFIG_DNET_AUTONEG_TIMEOUT
-#define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */
-#endif
-
-#include <net.h>
-#include <malloc.h>
-#include <linux/mii.h>
-
-#include <miiphy.h>
-#include <asm/io.h>
-#include <asm/unaligned.h>
-
-#include "dnet.h"
-
-struct dnet_device {
- struct dnet_registers *regs;
- const struct device *dev;
- struct eth_device netdev;
- unsigned short phy_addr;
-};
-
-/* get struct dnet_device from given struct netdev */
-#define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev)
-
-/* function for reading internal MAC register */
-u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg)
-{
- u16 data_read;
-
- /* issue a read */
- writel(reg, &dnet->regs->MACREG_ADDR);
-
- /* since a read/write op to the MAC is very slow,
- * we must wait before reading the data */
- udelay(1);
-
- /* read data read from the MAC register */
- data_read = readl(&dnet->regs->MACREG_DATA);
-
- /* all done */
- return data_read;
-}
-
-/* function for writing internal MAC register */
-void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val)
-{
- /* load data to write */
- writel(val, &dnet->regs->MACREG_DATA);
-
- /* issue a write */
- writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR);
-
- /* since a read/write op to the MAC is very slow,
- * we must wait before exiting */
- udelay(1);
-}
-
-static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value)
-{
- u16 tmp;
-
- debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n",
- dnet->phy_addr, reg, value);
-
- while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
- DNET_INTERNAL_GMII_MNG_CMD_FIN))
- ;
-
- /* prepare for a write operation */
- tmp = (1 << 13);
-
- /* only 5 bits allowed for register offset */
- reg &= 0x1f;
-
- /* prepare reg_value for a write */
- tmp |= (dnet->phy_addr << 8);
- tmp |= reg;
-
- /* write data to write first */
- dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
-
- /* write control word */
- dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
-
- while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
- DNET_INTERNAL_GMII_MNG_CMD_FIN))
- ;
-}
-
-static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg)
-{
- u16 value;
-
- while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
- DNET_INTERNAL_GMII_MNG_CMD_FIN))
- ;
-
- /* only 5 bits allowed for register offset*/
- reg &= 0x1f;
-
- /* prepare reg_value for a read */
- value = (dnet->phy_addr << 8);
- value |= reg;
-
- /* write control word */
- dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
-
- /* wait for end of transfer */
- while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
- DNET_INTERNAL_GMII_MNG_CMD_FIN))
- ;
-
- value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG);
-
- debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n",
- dnet->phy_addr, reg, value);
-
- return value;
-}
-
-static int dnet_send(struct eth_device *netdev, void *packet, int length)
-{
- struct dnet_device *dnet = to_dnet(netdev);
- int i, wrsz;
- unsigned int *bufp;
- unsigned int tx_cmd;
-
- debug(DRIVERNAME "[%s] Sending %u bytes\n", __func__, length);
-
- bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC);
- wrsz = (u32)length + 3;
- wrsz += ((u32)packet) & 0x3;
- wrsz >>= 2;
- tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length;
-
- /* check if there is enough room for the current frame */
- if (wrsz < (DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT))) {
- for (i = 0; i < wrsz; i++)
- writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
- /*
- * inform MAC that a packet's written and ready
- * to be shipped out
- */
- writel(tx_cmd, &dnet->regs->TX_LEN_FIFO);
- } else {
- printf(DRIVERNAME "No free space (actual %d, required %d "
- "(words))\n", DNET_FIFO_SIZE -
- readl(&dnet->regs->TX_FIFO_WCNT), wrsz);
- }
-
- /* No one cares anyway */
- return 0;
-}
-
-
-static int dnet_recv(struct eth_device *netdev)
-{
- struct dnet_device *dnet = to_dnet(netdev);
- unsigned int *data_ptr;
- int pkt_len, poll, i;
- u32 cmd_word;
-
- debug("Waiting for pkt (polling)\n");
- poll = 50;
- while ((readl(&dnet->regs->RX_FIFO_WCNT) >> 16) == 0) {
- udelay(10); /* wait 10 usec */
- if (--poll == 0)
- return 0; /* no pkt available */
- }
-
- cmd_word = readl(&dnet->regs->RX_LEN_FIFO);
- pkt_len = cmd_word & 0xFFFF;
-
- debug("Got pkt with size %d bytes\n", pkt_len);
-
- if (cmd_word & 0xDF180000)
- printf("%s packet receive error %x\n", __func__, cmd_word);
-
- data_ptr = (unsigned int *)net_rx_packets[0];
-
- for (i = 0; i < (pkt_len + 3) >> 2; i++)
- *data_ptr++ = readl(&dnet->regs->RX_DATA_FIFO);
-
- /* ok + 5 ?? */
- net_process_received_packet(net_rx_packets[0], pkt_len + 5);
-
- return 0;
-}
-
-static void dnet_set_hwaddr(struct eth_device *netdev)
-{
- struct dnet_device *dnet = to_dnet(netdev);
- u16 tmp;
-
- tmp = get_unaligned_be16(netdev->enetaddr);
- dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
- tmp = get_unaligned_be16(&netdev->enetaddr[2]);
- dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
- tmp = get_unaligned_be16(&netdev->enetaddr[4]);
- dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
-}
-
-static void dnet_phy_reset(struct dnet_device *dnet)
-{
- struct eth_device *netdev = &dnet->netdev;
- int i;
- u16 status, adv;
-
- adv = ADVERTISE_CSMA | ADVERTISE_ALL;
- dnet_mdio_write(dnet, MII_ADVERTISE, adv);
- printf("%s: Starting autonegotiation...\n", netdev->name);
- dnet_mdio_write(dnet, MII_BMCR, (BMCR_ANENABLE
- | BMCR_ANRESTART));
-
- for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
- status = dnet_mdio_read(dnet, MII_BMSR);
- if (status & BMSR_ANEGCOMPLETE)
- break;
- udelay(100);
- }
-
- if (status & BMSR_ANEGCOMPLETE)
- printf("%s: Autonegotiation complete\n", netdev->name);
- else
- printf("%s: Autonegotiation timed out (status=0x%04x)\n",
- netdev->name, status);
-}
-
-static int dnet_phy_init(struct dnet_device *dnet)
-{
- struct eth_device *netdev = &dnet->netdev;
- u16 phy_id, status, adv, lpa;
- int media, speed, duplex;
- int i;
- u32 ctl_reg;
-
- /* Find a PHY */
- for (i = 0; i < 32; i++) {
- dnet->phy_addr = i;
- phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
- if (phy_id != 0xffff) {
- /* ok we found it */
- printf("Found PHY at address %d PHYID (%04x:%04x)\n",
- i, phy_id,
- dnet_mdio_read(dnet, MII_PHYSID2));
- break;
- }
- }
-
- /* Check if the PHY is up to snuff... */
- phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
- if (phy_id == 0xffff) {
- printf("%s: No PHY present\n", netdev->name);
- return -1;
- }
-
- status = dnet_mdio_read(dnet, MII_BMSR);
- if (!(status & BMSR_LSTATUS)) {
- /* Try to re-negotiate if we don't have link already. */
- dnet_phy_reset(dnet);
-
- for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
- status = dnet_mdio_read(dnet, MII_BMSR);
- if (status & BMSR_LSTATUS)
- break;
- udelay(100);
- }
- }
-
- if (!(status & BMSR_LSTATUS)) {
- printf("%s: link down (status: 0x%04x)\n",
- netdev->name, status);
- return -1;
- } else {
- adv = dnet_mdio_read(dnet, MII_ADVERTISE);
- lpa = dnet_mdio_read(dnet, MII_LPA);
- media = mii_nway_result(lpa & adv);
- speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
- ? 1 : 0);
- duplex = (media & ADVERTISE_FULL) ? 1 : 0;
- /* 1000BaseT ethernet is not supported */
- printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
- netdev->name,
- speed ? "100" : "10",
- duplex ? "full" : "half",
- lpa);
-
- ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
-
- if (duplex)
- ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
- else
- ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
-
- dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
-
- return 0;
- }
-}
-
-static int dnet_init(struct eth_device *netdev, struct bd_info *bd)
-{
- struct dnet_device *dnet = to_dnet(netdev);
- u32 config;
-
- /*
- * dnet_halt should have been called at some point before now,
- * so we'll assume the controller is idle.
- */
-
- /* set hardware address */
- dnet_set_hwaddr(netdev);
-
- if (dnet_phy_init(dnet) < 0)
- return -1;
-
- /* flush rx/tx fifos */
- writel(DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
- &dnet->regs->SYS_CTL);
- udelay(1000);
- writel(0, &dnet->regs->SYS_CTL);
-
- config = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
-
- config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
- DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
- DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
- DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
-
- dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, config);
-
- /* Enable TX and RX */
- dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG,
- DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
-
- return 0;
-}
-
-static void dnet_halt(struct eth_device *netdev)
-{
- struct dnet_device *dnet = to_dnet(netdev);
-
- /* Disable TX and RX */
- dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, 0);
-}
-
-int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr)
-{
- struct dnet_device *dnet;
- struct eth_device *netdev;
- unsigned int dev_capa;
-
- dnet = malloc(sizeof(struct dnet_device));
- if (!dnet) {
- printf("Error: Failed to allocate memory for DNET%d\n", id);
- return -1;
- }
- memset(dnet, 0, sizeof(struct dnet_device));
-
- netdev = &dnet->netdev;
-
- dnet->regs = (struct dnet_registers *)regs;
- dnet->phy_addr = phy_addr;
-
- sprintf(netdev->name, "dnet%d", id);
- netdev->init = dnet_init;
- netdev->halt = dnet_halt;
- netdev->send = dnet_send;
- netdev->recv = dnet_recv;
-
- dev_capa = readl(&dnet->regs->VERCAPS) & 0xFFFF;
- debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev->name,
- (dev_capa & DNET_HAS_MDIO) ? "" : "no ",
- (dev_capa & DNET_HAS_IRQ) ? "" : "no ",
- (dev_capa & DNET_HAS_GIGABIT) ? "" : "no ",
- (dev_capa & DNET_HAS_DMA) ? "" : "no ");
-
- eth_register(netdev);
-
- return 0;
-}
diff --git a/drivers/net/dnet.h b/drivers/net/dnet.h
deleted file mode 100644
index fdb4fd2d391a..000000000000
--- a/drivers/net/dnet.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Dave Ethernet Controller driver
- *
- * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DRIVERS_DNET_H__
-#define __DRIVERS_DNET_H__
-
-#define DRIVERNAME "dnet"
-
-struct dnet_registers {
- /* ALL DNET FIFO REGISTERS */
- u32 RX_LEN_FIFO;
- u32 RX_DATA_FIFO;
- u32 TX_LEN_FIFO;
- u32 TX_DATA_FIFO;
- u32 pad1[0x3c];
- /* ALL DNET CONTROL/STATUS REGISTERS */
- u32 VERCAPS;
- u32 INTR_SRC;
- u32 INTR_ENB;
- u32 RX_STATUS;
- u32 TX_STATUS;
- u32 RX_FRAMES_CNT;
- u32 TX_FRAMES_CNT;
- u32 RX_FIFO_TH;
- u32 TX_FIFO_TH;
- u32 SYS_CTL;
- u32 PAUSE_TMR;
- u32 RX_FIFO_WCNT;
- u32 TX_FIFO_WCNT;
- u32 pad2[0x33];
- /* ALL DNET MAC REGISTERS */
- u32 MACREG_DATA; /* Mac-Reg Data */
- u32 MACREG_ADDR; /* Mac-Reg Addr */
- u32 pad3[0x3e];
- /* ALL DNET RX STATISTICS COUNTERS */
- u32 RX_PKT_IGNR_CNT;
- u32 RX_LEN_CHK_ERR_CNT;
- u32 RX_LNG_FRM_CNT;
- u32 RX_SHRT_FRM_CNT;
- u32 RX_IPG_VIOL_CNT;
- u32 RX_CRC_ERR_CNT;
- u32 RX_OK_PKT_CNT;
- u32 RX_CTL_FRM_CNT;
- u32 RX_PAUSE_FRM_CNT;
- u32 RX_MULTICAST_CNT;
- u32 RX_BROADCAST_CNT;
- u32 RX_VLAN_TAG_CNT;
- u32 RX_PRE_SHRINK_CNT;
- u32 RX_DRIB_NIB_CNT;
- u32 RX_UNSUP_OPCD_CNT;
- u32 RX_BYTE_CNT;
- u32 pad4[0x30];
- /* DNET TX STATISTICS COUNTERS */
- u32 TX_UNICAST_CNT;
- u32 TX_PAUSE_FRM_CNT;
- u32 TX_MULTICAST_CNT;
- u32 TX_BRDCAST_CNT;
- u32 TX_VLAN_TAG_CNT;
- u32 TX_BAD_FCS_CNT;
- u32 TX_JUMBO_CNT;
- u32 TX_BYTE_CNT;
-};
-
-/* SOME INTERNAL MAC-CORE REGISTER */
-#define DNET_INTERNAL_MODE_REG 0x0
-#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
-#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
-#define DNET_INTERNAL_IGP_REG 0x8
-#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
-#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
-#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
-#define DNET_INTERNAL_TX_RX_STS_REG 0x12
-#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
-#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
-
-#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
-
-#define DNET_INTERNAL_WRITE (1 << 31)
-
-/* MAC-CORE REGISTER FIELDS */
-
-/* MAC-CORE MODE REGISTER FIELDS */
-#define DNET_INTERNAL_MODE_GBITEN (1 << 0)
-#define DNET_INTERNAL_MODE_FCEN (1 << 1)
-#define DNET_INTERNAL_MODE_RXEN (1 << 2)
-#define DNET_INTERNAL_MODE_TXEN (1 << 3)
-
-/* MAC-CORE RXTX CONTROL REGISTER FIELDS */
-#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
-#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
-#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
-#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
-#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
-#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
-#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
-#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
-#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
-
-/* SYSTEM CONTROL REGISTER FIELDS */
-#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
-#define DNET_SYS_CTL_SENDPAUSE (1 << 2)
-#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
-#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
-
-/* TX STATUS REGISTER FIELDS */
-#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
-#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
-
-/* INTERRUPT SOURCE REGISTER FIELDS */
-#define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
-#define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
-#define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
-#define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
-#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
-#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
-#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
-#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
-#define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
-#define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
-#define DNET_INTR_SRC_PHY (1 << 19)
-
-/* INTERRUPT ENABLE REGISTER FIELDS */
-#define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
-#define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
-#define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
-#define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
-#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
-#define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
-#define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
-#define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
-#define DNET_INTR_ENB_RX_ERROR (1 << 11)
-#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
-#define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
-#define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
-#define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
-#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
-
-/*
- * Capabilities. Used by the driver to know the capabilities that
- * the ethernet controller inside the FPGA have.
- */
-
-#define DNET_HAS_MDIO (1 << 0)
-#define DNET_HAS_IRQ (1 << 1)
-#define DNET_HAS_GIGABIT (1 << 2)
-#define DNET_HAS_DMA (1 << 3)
-
-#define DNET_HAS_MII (1 << 4) /* or GMII */
-#define DNET_HAS_RMII (1 << 5) /* or RGMII */
-
-#define DNET_CAPS_MASK 0xFFFF
-
-#define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */
-#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
-#define DNET_FIFO_TX_DATA_AE_TH (384)
-
-#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
-
-#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 05/10] net: Remove ftmac110 driver
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
` (2 preceding siblings ...)
2022-03-31 17:46 ` [PATCH 04/10] net: Remove dnet driver Tom Rini
@ 2022-03-31 17:46 ` Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 06/10] net: Remove lan91c96 driver Tom Rini
` (5 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
This driver is not enabled by any board and not converted to DM_ETH.
Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/net/Makefile | 1 -
drivers/net/ftmac110.c | 491 -----------------------------------------
drivers/net/ftmac110.h | 175 ---------------
3 files changed, 667 deletions(-)
delete mode 100644 drivers/net/ftmac110.c
delete mode 100644 drivers/net/ftmac110.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 1fcd1b2d0b8d..4c4fe9b0b396 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -43,7 +43,6 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-$(CONFIG_FTGMAC100) += ftgmac100.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
-obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
deleted file mode 100644
index 7e54d4642ddf..000000000000
--- a/drivers/net/ftmac110.c
+++ /dev/null
@@ -1,491 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Faraday 10/100Mbps Ethernet Controller
- *
- * (C) Copyright 2013 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/cache.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <linux/dma-mapping.h>
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-#include "ftmac110.h"
-
-#define CFG_RXDES_NUM 8
-#define CFG_TXDES_NUM 2
-#define CFG_XBUF_SIZE 1536
-
-#define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
-#define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
-#define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
-
-/*
- * FTMAC110 DMA design issue
- *
- * Its DMA engine has a weird restriction that its Rx DMA engine
- * accepts only 16-bits aligned address, 32-bits aligned is not
- * acceptable. However this restriction does not apply to Tx DMA.
- *
- * Conclusion:
- * (1) Tx DMA Buffer Address:
- * 1 bytes aligned: Invalid
- * 2 bytes aligned: O.K
- * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
- * (2) Rx DMA Buffer Address:
- * 1 bytes aligned: Invalid
- * 2 bytes aligned: O.K
- * 4 bytes aligned: Invalid
- */
-
-struct ftmac110_chip {
- void __iomem *regs;
- uint32_t imr;
- uint32_t maccr;
- uint32_t lnkup;
- uint32_t phy_addr;
-
- struct ftmac110_desc *rxd;
- ulong rxd_dma;
- uint32_t rxd_idx;
-
- struct ftmac110_desc *txd;
- ulong txd_dma;
- uint32_t txd_idx;
-};
-
-static int ftmac110_reset(struct eth_device *dev);
-
-static uint16_t mdio_read(struct eth_device *dev,
- uint8_t phyaddr, uint8_t phyreg)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
- uint32_t tmp, ts;
- uint16_t ret = 0xffff;
-
- tmp = PHYCR_READ
- | (phyaddr << PHYCR_ADDR_SHIFT)
- | (phyreg << PHYCR_REG_SHIFT);
-
- writel(tmp, ®s->phycr);
-
- for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
- tmp = readl(®s->phycr);
- if (tmp & PHYCR_READ)
- continue;
- break;
- }
-
- if (tmp & PHYCR_READ)
- printf("ftmac110: mdio read timeout\n");
- else
- ret = (uint16_t)(tmp & 0xffff);
-
- return ret;
-}
-
-static void mdio_write(struct eth_device *dev,
- uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
- uint32_t tmp, ts;
-
- tmp = PHYCR_WRITE
- | (phyaddr << PHYCR_ADDR_SHIFT)
- | (phyreg << PHYCR_REG_SHIFT);
-
- writel(phydata, ®s->phydr);
- writel(tmp, ®s->phycr);
-
- for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
- if (readl(®s->phycr) & PHYCR_WRITE)
- continue;
- break;
- }
-
- if (readl(®s->phycr) & PHYCR_WRITE)
- printf("ftmac110: mdio write timeout\n");
-}
-
-static uint32_t ftmac110_phyqry(struct eth_device *dev)
-{
- ulong ts;
- uint32_t maccr;
- uint16_t pa, tmp, bmsr, bmcr;
- struct ftmac110_chip *chip = dev->priv;
-
- /* Default = 100Mbps Full */
- maccr = MACCR_100M | MACCR_FD;
-
- /* 1. find the phy device */
- for (pa = 0; pa < 32; ++pa) {
- tmp = mdio_read(dev, pa, MII_PHYSID1);
- if (tmp == 0xFFFF || tmp == 0x0000)
- continue;
- chip->phy_addr = pa;
- break;
- }
- if (pa >= 32) {
- puts("ftmac110: phy device not found!\n");
- goto exit;
- }
-
- /* 2. wait until link-up & auto-negotiation complete */
- chip->lnkup = 0;
- bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
- ts = get_timer(0);
- do {
- bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
- chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
- if (!chip->lnkup)
- continue;
- if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
- break;
- } while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
- if (!chip->lnkup) {
- puts("ftmac110: link down\n");
- goto exit;
- }
- if (!(bmcr & BMCR_ANENABLE))
- puts("ftmac110: auto negotiation disabled\n");
- else if (!(bmsr & BMSR_ANEGCOMPLETE))
- puts("ftmac110: auto negotiation timeout\n");
-
- /* 3. derive MACCR */
- if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
- tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
- tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
- if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
- maccr = MACCR_100M | MACCR_FD;
- else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
- maccr = MACCR_100M;
- else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
- maccr = MACCR_FD;
- else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
- maccr = 0;
- } else {
- if (bmcr & BMCR_SPEED100)
- maccr = MACCR_100M;
- else
- maccr = 0;
- if (bmcr & BMCR_FULLDPLX)
- maccr |= MACCR_FD;
- }
-
-exit:
- printf("ftmac110: %d Mbps, %s\n",
- (maccr & MACCR_100M) ? 100 : 10,
- (maccr & MACCR_FD) ? "Full" : "half");
- return maccr;
-}
-
-static int ftmac110_reset(struct eth_device *dev)
-{
- uint8_t *a;
- uint32_t i, maccr;
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
-
- /* 1. MAC reset */
- writel(MACCR_RESET, ®s->maccr);
- for (i = get_timer(0); get_timer(i) < 1000; ) {
- if (readl(®s->maccr) & MACCR_RESET)
- continue;
- break;
- }
- if (readl(®s->maccr) & MACCR_RESET) {
- printf("ftmac110: reset failed\n");
- return -ENXIO;
- }
-
- /* 1-1. Init tx ring */
- for (i = 0; i < CFG_TXDES_NUM; ++i) {
- /* owned by SW */
- chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK);
- }
- chip->txd_idx = 0;
-
- /* 1-2. Init rx ring */
- for (i = 0; i < CFG_RXDES_NUM; ++i) {
- /* owned by HW */
- chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK);
- chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER);
- }
- chip->rxd_idx = 0;
-
- /* 2. PHY status query */
- maccr = ftmac110_phyqry(dev);
-
- /* 3. Fix up the MACCR value */
- chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
- | MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;
-
- /* 4. MAC address setup */
- a = dev->enetaddr;
- writel(a[1] | (a[0] << 8), ®s->mac[0]);
- writel(a[5] | (a[4] << 8) | (a[3] << 16)
- | (a[2] << 24), ®s->mac[1]);
-
- /* 5. MAC registers setup */
- writel(chip->rxd_dma, ®s->rxba);
- writel(chip->txd_dma, ®s->txba);
- /* interrupt at each tx/rx */
- writel(ITC_DEFAULT, ®s->itc);
- /* no tx pool, rx poll = 1 normal cycle */
- writel(APTC_DEFAULT, ®s->aptc);
- /* rx threshold = [6/8 fifo, 2/8 fifo] */
- writel(DBLAC_DEFAULT, ®s->dblac);
- /* disable & clear all interrupt status */
- chip->imr = 0;
- writel(ISR_ALL, ®s->isr);
- writel(chip->imr, ®s->imr);
- /* enable mac */
- writel(chip->maccr, ®s->maccr);
-
- return 0;
-}
-
-static int ftmac110_probe(struct eth_device *dev, struct bd_info *bis)
-{
- debug("ftmac110: probe\n");
-
- if (ftmac110_reset(dev))
- return -1;
-
- return 0;
-}
-
-static void ftmac110_halt(struct eth_device *dev)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
-
- writel(0, ®s->imr);
- writel(0, ®s->maccr);
-
- debug("ftmac110: halt\n");
-}
-
-static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_regs *regs = chip->regs;
- struct ftmac110_desc *txd;
- uint64_t ctrl;
-
- if (!chip->lnkup)
- return 0;
-
- if (len <= 0 || len > CFG_XBUF_SIZE) {
- printf("ftmac110: bad tx pkt len(%d)\n", len);
- return 0;
- }
-
- len = max(60, len);
-
- txd = &chip->txd[chip->txd_idx];
- ctrl = le64_to_cpu(txd->ctrl);
- if (ctrl & FTMAC110_TXD_OWNER) {
- /* kick-off Tx DMA */
- writel(0xffffffff, ®s->txpd);
- printf("ftmac110: out of txd\n");
- return 0;
- }
-
- memcpy(txd->vbuf, (void *)pkt, len);
- dma_map_single(txd->vbuf, len, DMA_TO_DEVICE);
-
- /* clear control bits */
- ctrl &= FTMAC110_TXD_CLRMASK;
- /* set len, fts and lts */
- ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS;
- /* set owner bit */
- ctrl |= FTMAC110_TXD_OWNER;
- /* write back to descriptor */
- txd->ctrl = cpu_to_le64(ctrl);
-
- /* kick-off Tx DMA */
- writel(0xffffffff, ®s->txpd);
-
- chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
-
- return len;
-}
-
-static int ftmac110_recv(struct eth_device *dev)
-{
- struct ftmac110_chip *chip = dev->priv;
- struct ftmac110_desc *rxd;
- uint32_t len, rlen = 0;
- uint64_t ctrl;
- uint8_t *buf;
-
- if (!chip->lnkup)
- return 0;
-
- do {
- rxd = &chip->rxd[chip->rxd_idx];
- ctrl = le64_to_cpu(rxd->ctrl);
- if (ctrl & FTMAC110_RXD_OWNER)
- break;
-
- len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
- buf = rxd->vbuf;
-
- if (ctrl & FTMAC110_RXD_ERRMASK) {
- printf("ftmac110: rx error\n");
- } else {
- dma_map_single(buf, len, DMA_FROM_DEVICE);
- net_process_received_packet(buf, len);
- rlen += len;
- }
-
- /* owned by hardware */
- ctrl &= FTMAC110_RXD_CLRMASK;
- ctrl |= FTMAC110_RXD_OWNER;
- rxd->ctrl |= cpu_to_le64(ctrl);
-
- chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
- } while (0);
-
- return rlen;
-}
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-
-static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad,
- int reg)
-{
- uint16_t value = 0;
- int ret = 0;
- struct eth_device *dev;
-
- dev = eth_get_dev_by_name(bus->name);
- if (dev == NULL) {
- printf("%s: no such device\n", bus->name);
- ret = -1;
- } else {
- value = mdio_read(dev, addr, reg);
- }
-
- if (ret < 0)
- return ret;
- return value;
-}
-
-static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
- int reg, u16 value)
-{
- int ret = 0;
- struct eth_device *dev;
-
- dev = eth_get_dev_by_name(bus->name);
- if (dev == NULL) {
- printf("%s: no such device\n", bus->name);
- ret = -1;
- } else {
- mdio_write(dev, addr, reg, value);
- }
-
- return ret;
-}
-
-#endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
-
-int ftmac110_initialize(struct bd_info *bis)
-{
- int i, card_nr = 0;
- struct eth_device *dev;
- struct ftmac110_chip *chip;
-
- dev = malloc(sizeof(*dev) + sizeof(*chip));
- if (dev == NULL) {
- panic("ftmac110: out of memory 1\n");
- return -1;
- }
- chip = (struct ftmac110_chip *)(dev + 1);
- memset(dev, 0, sizeof(*dev) + sizeof(*chip));
-
- sprintf(dev->name, "FTMAC110#%d", card_nr);
-
- dev->iobase = CONFIG_FTMAC110_BASE;
- chip->regs = (void __iomem *)dev->iobase;
- dev->priv = chip;
- dev->init = ftmac110_probe;
- dev->halt = ftmac110_halt;
- dev->send = ftmac110_send;
- dev->recv = ftmac110_recv;
-
- /* allocate tx descriptors (it must be 16 bytes aligned) */
- chip->txd = dma_alloc_coherent(
- sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma);
- if (!chip->txd)
- panic("ftmac110: out of memory 3\n");
- memset(chip->txd, 0,
- sizeof(struct ftmac110_desc) * CFG_TXDES_NUM);
- for (i = 0; i < CFG_TXDES_NUM; ++i) {
- void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
-
- if (!va)
- panic("ftmac110: out of memory 4\n");
- chip->txd[i].vbuf = va;
- chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va));
- chip->txd[i].ctrl = 0; /* owned by SW */
- }
- chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END);
- chip->txd_idx = 0;
-
- /* allocate rx descriptors (it must be 16 bytes aligned) */
- chip->rxd = dma_alloc_coherent(
- sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma);
- if (!chip->rxd)
- panic("ftmac110: out of memory 4\n");
- memset((void *)chip->rxd, 0,
- sizeof(struct ftmac110_desc) * CFG_RXDES_NUM);
- for (i = 0; i < CFG_RXDES_NUM; ++i) {
- void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
-
- if (!va)
- panic("ftmac110: out of memory 5\n");
- /* it needs to be exactly 2 bytes aligned */
- va = ((uint8_t *)va + 2);
- chip->rxd[i].vbuf = va;
- chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va));
- chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER
- | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE));
- }
- chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END);
- chip->rxd_idx = 0;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = ftmac110_mdio_read;
- mdiodev->write = ftmac110_mdio_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
-
- card_nr++;
-
- return card_nr;
-}
diff --git a/drivers/net/ftmac110.h b/drivers/net/ftmac110.h
deleted file mode 100644
index a792b515b446..000000000000
--- a/drivers/net/ftmac110.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Faraday 10/100Mbps Ethernet Controller
- *
- * (C) Copyright 2013 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- */
-
-#ifndef _FTMAC110_H
-#define _FTMAC110_H
-
-struct ftmac110_regs {
- uint32_t isr; /* 0x00: Interrups Status Register */
- uint32_t imr; /* 0x04: Interrupt Mask Register */
- uint32_t mac[2]; /* 0x08: MAC Address */
- uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */
- uint32_t txpd; /* 0x18: Tx Poll Demand Register */
- uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */
- uint32_t txba; /* 0x20: Tx Ring Base Address Register */
- uint32_t rxba; /* 0x24: Rx Ring Base Address Register */
- uint32_t itc; /* 0x28: Interrupt Timer Control Register */
- uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */
- uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */
- uint32_t revr; /* 0x34: Revision Register */
- uint32_t fear; /* 0x38: Feature Register */
- uint32_t rsvd[19];
- uint32_t maccr; /* 0x88: MAC Control Register */
- uint32_t macsr; /* 0x8C: MAC Status Register */
- uint32_t phycr; /* 0x90: PHY Control Register */
- uint32_t phydr; /* 0x94: PHY Data Register */
- uint32_t fcr; /* 0x98: Flow Control Register */
- uint32_t bpr; /* 0x9C: Back Pressure Register */
-};
-
-/*
- * Interrupt status/mask register(ISR/IMR) bits
- */
-#define ISR_ALL 0x3ff
-#define ISR_PHYSTCHG (1 << 9) /* phy status change */
-#define ISR_AHBERR (1 << 8) /* bus error */
-#define ISR_RXLOST (1 << 7) /* rx lost */
-#define ISR_RXFIFO (1 << 6) /* rx to fifo */
-#define ISR_TXLOST (1 << 5) /* tx lost */
-#define ISR_TXOK (1 << 4) /* tx to ethernet */
-#define ISR_NOTXBUF (1 << 3) /* out of tx buffer */
-#define ISR_TXFIFO (1 << 2) /* tx to fifo */
-#define ISR_NORXBUF (1 << 1) /* out of rx buffer */
-#define ISR_RXOK (1 << 0) /* rx to buffer */
-
-/*
- * MACCR control bits
- */
-#define MACCR_100M (1 << 18) /* 100Mbps mode */
-#define MACCR_RXBCST (1 << 17) /* rx broadcast packet */
-#define MACCR_RXMCST (1 << 16) /* rx multicast packet */
-#define MACCR_FD (1 << 15) /* full duplex */
-#define MACCR_CRCAPD (1 << 14) /* tx crc append */
-#define MACCR_RXALL (1 << 12) /* rx all packets */
-#define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */
-#define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */
-#define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */
-#define MACCR_RXEN (1 << 8) /* rx enable */
-#define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */
-#define MACCR_TXEN (1 << 5) /* tx enable */
-#define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */
-#define MACCR_LOOPBACK (1 << 3) /* loop-back */
-#define MACCR_RESET (1 << 2) /* reset */
-#define MACCR_RXDMAEN (1 << 1) /* rx dma enable */
-#define MACCR_TXDMAEN (1 << 0) /* tx dma enable */
-
-/*
- * PHYCR control bits
- */
-#define PHYCR_READ (1 << 26)
-#define PHYCR_WRITE (1 << 27)
-#define PHYCR_REG_SHIFT 21
-#define PHYCR_ADDR_SHIFT 16
-
-/*
- * ITC control bits
- */
-
-/* Tx Cycle Length */
-#define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */
-#define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */
-/* Tx Threshold: Aggregate n interrupts as 1 interrupt */
-#define ITC_TX_THR(n) (((n) & 0x7) << 12)
-/* Tx Interrupt Timeout = n * Tx Cycle */
-#define ITC_TX_ITMO(n) (((n) & 0xf) << 8)
-/* Rx Cycle Length */
-#define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */
-#define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */
-/* Rx Threshold: Aggregate n interrupts as 1 interrupt */
-#define ITC_RX_THR(n) (((n) & 0x7) << 4)
-/* Rx Interrupt Timeout = n * Rx Cycle */
-#define ITC_RX_ITMO(n) (((n) & 0xf) << 0)
-
-#define ITC_DEFAULT \
- (ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0))
-
-/*
- * APTC contrl bits
- */
-
-/* Tx Cycle Length */
-#define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */
-#define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */
-/* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */
-#define APTC_TX_PTMO(n) (((n) & 0xf) << 8)
-/* Rx Cycle Length */
-#define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */
-#define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */
-/* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */
-#define APTC_RX_PTMO(n) (((n) & 0xf) << 0)
-
-#define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1))
-
-/*
- * DBLAC contrl bits
- */
-#define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */
-#define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */
-#define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */
-#define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */
-#define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */
-#define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */
-#define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */
-#define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */
-#define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */
-
-#define DBLAC_DEFAULT \
- (DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2))
-
-/*
- * descriptor structure
- */
-struct ftmac110_desc {
- uint64_t ctrl;
- uint32_t pbuf;
- void *vbuf;
-};
-
-#define FTMAC110_RXD_END ((uint64_t)1 << 63)
-#define FTMAC110_RXD_BUFSZ(x) (((uint64_t)(x) & 0x7ff) << 32)
-
-#define FTMAC110_RXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */
-#define FTMAC110_RXD_FRS ((uint64_t)1 << 29) /* first pkt desc */
-#define FTMAC110_RXD_LRS ((uint64_t)1 << 28) /* last pkt desc */
-#define FTMAC110_RXD_ODDNB ((uint64_t)1 << 22) /* odd nibble */
-#define FTMAC110_RXD_RUNT ((uint64_t)1 << 21) /* runt pkt */
-#define FTMAC110_RXD_FTL ((uint64_t)1 << 20) /* frame too long */
-#define FTMAC110_RXD_CRC ((uint64_t)1 << 19) /* pkt crc error */
-#define FTMAC110_RXD_ERR ((uint64_t)1 << 18) /* bus error */
-#define FTMAC110_RXD_ERRMASK ((uint64_t)0x1f << 18)
-#define FTMAC110_RXD_BCST ((uint64_t)1 << 17) /* Bcst pkt */
-#define FTMAC110_RXD_MCST ((uint64_t)1 << 16) /* Mcst pkt */
-#define FTMAC110_RXD_LEN(x) ((uint64_t)((x) & 0x7ff))
-
-#define FTMAC110_RXD_CLRMASK \
- (FTMAC110_RXD_END | FTMAC110_RXD_BUFSZ(0x7ff))
-
-#define FTMAC110_TXD_END ((uint64_t)1 << 63) /* end of ring */
-#define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */
-#define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */
-#define FTMAC110_TXD_FTS ((uint64_t)1 << 60) /* first pkt desc */
-#define FTMAC110_TXD_LTS ((uint64_t)1 << 59) /* last pkt desc */
-#define FTMAC110_TXD_LEN(x) ((uint64_t)((x) & 0x7ff) << 32)
-
-#define FTMAC110_TXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */
-#define FTMAC110_TXD_COL ((uint64_t)3) /* collision */
-
-#define FTMAC110_TXD_CLRMASK \
- (FTMAC110_TXD_END)
-
-#endif /* FTMAC110_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 06/10] net: Remove lan91c96 driver
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
` (3 preceding siblings ...)
2022-03-31 17:46 ` [PATCH 05/10] net: Remove ftmac110 driver Tom Rini
@ 2022-03-31 17:46 ` Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 07/10] net: Remove natsemi driver Tom Rini
` (4 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
This driver is not enabled by any board and not converted to DM_ETH.
Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/net/Makefile | 1 -
drivers/net/lan91c96.c | 799 -----------------------------------------
drivers/net/lan91c96.h | 616 -------------------------------
3 files changed, 1416 deletions(-)
delete mode 100644 drivers/net/lan91c96.c
delete mode 100644 drivers/net/lan91c96.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4c4fe9b0b396..be3264e04133 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -47,7 +47,6 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_KSZ9477) += ksz9477.o
-obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c
deleted file mode 100644
index c2f611144db6..000000000000
--- a/drivers/net/lan91c96.c
+++ /dev/null
@@ -1,799 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*------------------------------------------------------------------------
- * lan91c96.c
- * This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based
- * on the SMC91111 driver from U-Boot.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Rolf Offermanns <rof@sysgo.de>
- *
- * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- * Developed by Simple Network Magic Corporation (SNMC)
- * Copyright (C) 1996 by Erik Stahlman (ES)
- *
- * Information contained in this file was obtained from the LAN91C96
- * manual from SMC. To get a copy, if you really want one, you can find
- * information under www.smsc.com.
- *
- * "Features" of the SMC chip:
- * 6144 byte packet memory. ( for the 91C96 )
- * EEPROM for configuration
- * AUI/TP selection ( mine has 10Base2/10BaseT select )
- *
- * Arguments:
- * io = for the base address
- * irq = for the IRQ
- *
- * author:
- * Erik Stahlman ( erik@vt.edu )
- * Daris A Nevil ( dnevil@snmc.com )
- *
- *
- * Hardware multicast code from Peter Cammaert ( pc@denkart.be )
- *
- * Sources:
- * o SMSC LAN91C96 databook (www.smsc.com)
- * o smc91111.c (u-boot driver)
- * o smc9194.c (linux kernel driver)
- * o lan91c96.c (Intel Diagnostic Manager driver)
- *
- * History:
- * 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version)
- * for lan91c96
- *---------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <malloc.h>
-#include <linux/delay.h>
-#include "lan91c96.h"
-#include <net.h>
-#include <linux/compiler.h>
-
-/*------------------------------------------------------------------------
- *
- * Configuration options, for the experienced user to change.
- *
- -------------------------------------------------------------------------*/
-
-/* Use power-down feature of the chip */
-#define POWER_DOWN 0
-
-/*
- * Wait time for memory to be free. This probably shouldn't be
- * tuned that much, as waiting for this means nothing else happens
- * in the system
-*/
-#define MEMORY_WAIT_TIME 16
-
-#define SMC_DEBUG 0
-
-#if (SMC_DEBUG > 2 )
-#define PRINTK3(args...) printf(args)
-#else
-#define PRINTK3(args...)
-#endif
-
-#if SMC_DEBUG > 1
-#define PRINTK2(args...) printf(args)
-#else
-#define PRINTK2(args...)
-#endif
-
-#ifdef SMC_DEBUG
-#define PRINTK(args...) printf(args)
-#else
-#define PRINTK(args...)
-#endif
-
-
-/*------------------------------------------------------------------------
- *
- * The internal workings of the driver. If you are changing anything
- * here with the SMC stuff, you should have the datasheet and know
- * what you are doing.
- *
- *------------------------------------------------------------------------
- */
-#define DRIVER_NAME "LAN91C96"
-#define SMC_ALLOC_MAX_TRY 5
-#define SMC_TX_TIMEOUT 30
-
-#define ETH_ZLEN 60
-
-#ifdef CONFIG_LAN91C96_USE_32_BIT
-#define USE_32_BIT 1
-#else
-#undef USE_32_BIT
-#endif
-
-/* See if a MAC address is defined in the current environment. If so use it. If not
- . print a warning and set the environment and other globals with the default.
- . If an EEPROM is present it really should be consulted.
-*/
-static int smc_get_ethaddr(struct bd_info *bd, struct eth_device *dev);
-static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac);
-
-/* ------------------------------------------------------------
- * Internal routines
- * ------------------------------------------------------------
- */
-
-static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
-
-/*
- * This function must be called before smc_open() if you want to override
- * the default mac address.
- */
-
-static void smc_set_mac_addr(const unsigned char *addr)
-{
- int i;
-
- for (i = 0; i < sizeof (smc_mac_addr); i++) {
- smc_mac_addr[i] = addr[i];
- }
-}
-
-/***********************************************
- * Show available memory *
- ***********************************************/
-void dump_memory_info(struct eth_device *dev)
-{
- __maybe_unused word mem_info;
- word old_bank;
-
- old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT) & 0xF;
-
- SMC_SELECT_BANK(dev, 0);
- mem_info = SMC_inw(dev, LAN91C96_MIR);
- PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048);
-
- SMC_SELECT_BANK(dev, old_bank);
-}
-
-/*
- * A rather simple routine to print out a packet for debugging purposes.
- */
-#if SMC_DEBUG > 2
-static void print_packet (byte *, int);
-#endif
-
-static int poll4int (struct eth_device *dev, byte mask, int timeout)
-{
- int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
- int is_timeout = 0;
- word old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT);
-
- PRINTK2 ("Polling...\n");
- SMC_SELECT_BANK(dev, 2);
- while ((SMC_inw(dev, LAN91C96_INT_STATS) & mask) == 0) {
- if (get_timer (0) >= tmo) {
- is_timeout = 1;
- break;
- }
- }
-
- /* restore old bank selection */
- SMC_SELECT_BANK(dev, old_bank);
-
- if (is_timeout)
- return 1;
- else
- return 0;
-}
-
-/*
- * Function: smc_reset
- * Purpose:
- * This sets the SMC91111 chip to its normal state, hopefully from whatever
- * mess that any other DOS driver has put it in.
- *
- * Maybe I should reset more registers to defaults in here? SOFTRST should
- * do that for me.
- *
- * Method:
- * 1. send a SOFT RESET
- * 2. wait for it to finish
- * 3. enable autorelease mode
- * 4. reset the memory management unit
- * 5. clear all interrupts
- *
-*/
-static void smc_reset(struct eth_device *dev)
-{
- PRINTK2("%s:smc_reset\n", dev->name);
-
- /* This resets the registers mostly to defaults, but doesn't
- affect EEPROM. That seems unnecessary */
- SMC_SELECT_BANK(dev, 0);
- SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
-
- udelay(10);
-
- /* Disable transmit and receive functionality */
- SMC_outw(dev, 0, LAN91C96_RCR);
- SMC_outw(dev, 0, LAN91C96_TCR);
-
- /* set the control register */
- SMC_SELECT_BANK(dev, 1);
- SMC_outw(dev, SMC_inw(dev, LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8,
- LAN91C96_CONTROL);
-
- /* Disable all interrupts */
- SMC_outb(dev, 0, LAN91C96_INT_MASK);
-}
-
-/*
- * Function: smc_enable
- * Purpose: let the chip talk to the outside work
- * Method:
- * 1. Initialize the Memory Configuration Register
- * 2. Enable the transmitter
- * 3. Enable the receiver
-*/
-static void smc_enable(struct eth_device *dev)
-{
- PRINTK2("%s:smc_enable\n", dev->name);
- SMC_SELECT_BANK(dev, 0);
-
- /* Initialize the Memory Configuration Register. See page
- 49 of the LAN91C96 data sheet for details. */
- SMC_outw(dev, LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR);
-
- /* Initialize the Transmit Control Register */
- SMC_outw(dev, LAN91C96_TCR_TXENA, LAN91C96_TCR);
- /* Initialize the Receive Control Register
- * FIXME:
- * The promiscuous bit set because I could not receive ARP reply
- * packets from the server when I send a ARP request. It only works
- * when I set the promiscuous bit
- */
- SMC_outw(dev, LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR);
-}
-
-/*
- * Function: smc_shutdown
- * Purpose: closes down the SMC91xxx chip.
- * Method:
- * 1. zero the interrupt mask
- * 2. clear the enable receive flag
- * 3. clear the enable xmit flags
- *
- * TODO:
- * (1) maybe utilize power down mode.
- * Why not yet? Because while the chip will go into power down mode,
- * the manual says that it will wake up in response to any I/O requests
- * in the register space. Empirical results do not show this working.
- */
-static void smc_shutdown(struct eth_device *dev)
-{
- PRINTK2("%s:smc_shutdown\n", dev->name);
-
- /* no more interrupts for me */
- SMC_SELECT_BANK(dev, 2);
- SMC_outb(dev, 0, LAN91C96_INT_MASK);
-
- /* and tell the card to stay away from that nasty outside world */
- SMC_SELECT_BANK(dev, 0);
- SMC_outb(dev, 0, LAN91C96_RCR);
- SMC_outb(dev, 0, LAN91C96_TCR);
-}
-
-
-/*
- * Function: smc_hardware_send_packet(struct net_device * )
- * Purpose:
- * This sends the actual packet to the SMC9xxx chip.
- *
- * Algorithm:
- * First, see if a saved_skb is available.
- * ( this should NOT be called if there is no 'saved_skb'
- * Now, find the packet number that the chip allocated
- * Point the data pointers at it in memory
- * Set the length word in the chip's memory
- * Dump the packet to chip memory
- * Check if a last byte is needed ( odd length packet )
- * if so, set the control flag right
- * Tell the card to send it
- * Enable the transmit interrupt, so I know if it failed
- * Free the kernel data if I actually sent it.
- */
-static int smc_send_packet(struct eth_device *dev, void *packet,
- int packet_length)
-{
- byte packet_no;
- byte *buf;
- int length;
- int numPages;
- int try = 0;
- int time_out;
- byte status;
-
-
- PRINTK3("%s:smc_hardware_send_packet\n", dev->name);
-
- length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
-
- /* allocate memory
- ** The MMU wants the number of pages to be the number of 256 bytes
- ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
- **
- ** The 91C111 ignores the size bits, but the code is left intact
- ** for backwards and future compatibility.
- **
- ** Pkt size for allocating is data length +6 (for additional status
- ** words, length and ctl!)
- **
- ** If odd size then last byte is included in this header.
- */
- numPages = ((length & 0xfffe) + 6);
- numPages >>= 8; /* Divide by 256 */
-
- if (numPages > 7) {
- printf("%s: Far too big packet error. \n", dev->name);
- return 0;
- }
-
- /* now, try to allocate the memory */
-
- SMC_SELECT_BANK(dev, 2);
- SMC_outw(dev, LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU);
-
- again:
- try++;
- time_out = MEMORY_WAIT_TIME;
- do {
- status = SMC_inb(dev, LAN91C96_INT_STATS);
- if (status & LAN91C96_IST_ALLOC_INT) {
-
- SMC_outb(dev, LAN91C96_IST_ALLOC_INT,
- LAN91C96_INT_STATS);
- break;
- }
- } while (--time_out);
-
- if (!time_out) {
- PRINTK2 ("%s: memory allocation, try %d failed ...\n",
- dev->name, try);
- if (try < SMC_ALLOC_MAX_TRY)
- goto again;
- else
- return 0;
- }
-
- PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
- dev->name, try);
-
- /* I can send the packet now.. */
- buf = (byte *) packet;
-
- /* If I get here, I _know_ there is a packet slot waiting for me */
- packet_no = SMC_inb(dev, LAN91C96_ARR);
- if (packet_no & LAN91C96_ARR_FAILED) {
- /* or isn't there? BAD CHIP! */
- printf("%s: Memory allocation failed. \n", dev->name);
- return 0;
- }
-
- /* we have a packet address, so tell the card to use it */
- SMC_outb(dev, packet_no, LAN91C96_PNR);
-
- /* point to the beginning of the packet */
- SMC_outw(dev, LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
-
- PRINTK3("%s: Trying to xmit packet of length %x\n",
- dev->name, length);
-
-#if SMC_DEBUG > 2
- printf ("Transmitting Packet\n");
- print_packet (buf, length);
-#endif
-
- /* send the packet length ( +6 for status, length and ctl byte )
- and the status word ( set to zeros ) */
-#ifdef USE_32_BIT
- SMC_outl(dev, (length + 6) << 16, LAN91C96_DATA_HIGH);
-#else
- SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
- /* send the packet length ( +6 for status words, length, and ctl */
- SMC_outw(dev, (length + 6), LAN91C96_DATA_HIGH);
-#endif /* USE_32_BIT */
-
- /* send the actual data
- * I _think_ it's faster to send the longs first, and then
- * mop up by sending the last word. It depends heavily
- * on alignment, at least on the 486. Maybe it would be
- * a good idea to check which is optimal? But that could take
- * almost as much time as is saved?
- */
-#ifdef USE_32_BIT
- SMC_outsl(dev, LAN91C96_DATA_HIGH, buf, length >> 2);
- if (length & 0x2)
- SMC_outw(dev, *((word *) (buf + (length & 0xFFFFFFFC))),
- LAN91C96_DATA_HIGH);
-#else
- SMC_outsw(dev, LAN91C96_DATA_HIGH, buf, (length) >> 1);
-#endif /* USE_32_BIT */
-
- /* Send the last byte, if there is one. */
- if ((length & 1) == 0) {
- SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
- } else {
- SMC_outw(dev, buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH);
- }
-
- /* and let the chipset deal with it */
- SMC_outw(dev, LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU);
-
- /* poll for TX INT */
- if (poll4int (dev, LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) {
- /* sending failed */
- PRINTK2("%s: TX timeout, sending failed...\n", dev->name);
-
- /* release packet */
- SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
-
- /* wait for MMU getting ready (low) */
- while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay(10);
-
- PRINTK2("MMU ready\n");
-
-
- return 0;
- } else {
- /* ack. int */
- SMC_outw(dev, LAN91C96_IST_TX_INT, LAN91C96_INT_STATS);
-
- PRINTK2("%s: Sent packet of length %d \n", dev->name, length);
-
- /* release packet */
- SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
-
- /* wait for MMU getting ready (low) */
- while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay(10);
-
- PRINTK2 ("MMU ready\n");
- }
-
- return length;
-}
-
-
-/*
- * Open and Initialize the board
- *
- * Set up everything, reset the card, etc ..
- *
- */
-static int smc_open(struct bd_info *bd, struct eth_device *dev)
-{
- int i, err; /* used to set hw ethernet address */
-
- PRINTK2("%s:smc_open\n", dev->name);
-
- /* reset the hardware */
-
- smc_reset(dev);
- smc_enable(dev);
-
- SMC_SELECT_BANK(dev, 1);
- /* set smc_mac_addr, and sync it with u-boot globals */
- err = smc_get_ethaddr(bd, dev);
- if (err < 0)
- return -1;
-#ifdef USE_32_BIT
- for (i = 0; i < 6; i += 2) {
- word address;
-
- address = smc_mac_addr[i + 1] << 8;
- address |= smc_mac_addr[i];
- SMC_outw(dev, address, LAN91C96_IA0 + i);
- }
-#else
- for (i = 0; i < 6; i++)
- SMC_outb(dev, smc_mac_addr[i], LAN91C96_IA0 + i);
-#endif
- return 0;
-}
-
-/*-------------------------------------------------------------
- *
- * smc_rcv - receive a packet from the card
- *
- * There is ( at least ) a packet waiting to be read from
- * chip-memory.
- *
- * o Read the status
- * o If an error, record it
- * o otherwise, read in the packet
- *-------------------------------------------------------------
- */
-static int smc_rcv(struct eth_device *dev)
-{
- int packet_number;
- word status;
- word packet_length;
- int is_error = 0;
-
-#ifdef USE_32_BIT
- dword stat_len;
-#endif
-
-
- SMC_SELECT_BANK(dev, 2);
- packet_number = SMC_inw(dev, LAN91C96_FIFO);
-
- if (packet_number & LAN91C96_FIFO_RXEMPTY) {
- return 0;
- }
-
- PRINTK3("%s:smc_rcv\n", dev->name);
- /* start reading from the start of the packet */
- SMC_outw(dev, LAN91C96_PTR_READ | LAN91C96_PTR_RCV |
- LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
-
- /* First two words are status and packet_length */
-#ifdef USE_32_BIT
- stat_len = SMC_inl(dev, LAN91C96_DATA_HIGH);
- status = stat_len & 0xffff;
- packet_length = stat_len >> 16;
-#else
- status = SMC_inw(dev, LAN91C96_DATA_HIGH);
- packet_length = SMC_inw(dev, LAN91C96_DATA_HIGH);
-#endif
-
- packet_length &= 0x07ff; /* mask off top bits */
-
- PRINTK2 ("RCV: STATUS %4x LENGTH %4x\n", status, packet_length);
-
- if (!(status & FRAME_FILTER)) {
- /* Adjust for having already read the first two words */
- packet_length -= 4; /*4; */
-
-
- /* set odd length for bug in LAN91C111, */
- /* which never sets RS_ODDFRAME */
- /* TODO ? */
-
-
-#ifdef USE_32_BIT
- PRINTK3 (" Reading %d dwords (and %d bytes) \n",
- packet_length >> 2, packet_length & 3);
- /* QUESTION: Like in the TX routine, do I want
- to send the DWORDs or the bytes first, or some
- mixture. A mixture might improve already slow PIO
- performance */
- SMC_insl(dev, LAN91C96_DATA_HIGH, net_rx_packets[0],
- packet_length >> 2);
- /* read the left over bytes */
- if (packet_length & 3) {
- int i;
-
- byte *tail = (byte *)(net_rx_packets[0] +
- (packet_length & ~3));
- dword leftover = SMC_inl(dev, LAN91C96_DATA_HIGH);
-
- for (i = 0; i < (packet_length & 3); i++)
- *tail++ = (byte) (leftover >> (8 * i)) & 0xff;
- }
-#else
- PRINTK3(" Reading %d words and %d byte(s)\n",
- (packet_length >> 1), packet_length & 1);
- SMC_insw(dev, LAN91C96_DATA_HIGH, net_rx_packets[0],
- packet_length >> 1);
-
-#endif /* USE_32_BIT */
-
-#if SMC_DEBUG > 2
- printf ("Receiving Packet\n");
- print_packet((byte *)net_rx_packets[0], packet_length);
-#endif
- } else {
- /* error ... */
- /* TODO ? */
- is_error = 1;
- }
-
- while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay(1); /* Wait until not busy */
-
- /* error or good, tell the card to get rid of this packet */
- SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
-
- while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay(1); /* Wait until not busy */
-
- if (!is_error) {
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[0], packet_length);
- return packet_length;
- } else {
- return 0;
- }
-
-}
-
-/*----------------------------------------------------
- * smc_close
- *
- * this makes the board clean up everything that it can
- * and not talk to the outside world. Caused by
- * an 'ifconfig ethX down'
- *
- -----------------------------------------------------*/
-static int smc_close(struct eth_device *dev)
-{
- PRINTK2("%s:smc_close\n", dev->name);
-
- /* clear everything */
- smc_shutdown(dev);
-
- return 0;
-}
-
-#if SMC_DEBUG > 2
-static void print_packet(byte *buf, int length)
-{
-#if 0
- int i;
- int remainder;
- int lines;
-
- printf ("Packet of length %d \n", length);
-
- lines = length / 16;
- remainder = length % 16;
-
- for (i = 0; i < lines; i++) {
- int cur;
-
- for (cur = 0; cur < 8; cur++) {
- byte a, b;
-
- a = *(buf++);
- b = *(buf++);
- printf ("%02x%02x ", a, b);
- }
- printf ("\n");
- }
- for (i = 0; i < remainder / 2; i++) {
- byte a, b;
-
- a = *(buf++);
- b = *(buf++);
- printf ("%02x%02x ", a, b);
- }
- printf ("\n");
-#endif /* 0 */
-}
-#endif /* SMC_DEBUG > 2 */
-
-static int lan91c96_init(struct eth_device *dev, struct bd_info *bd)
-{
- return smc_open(bd, dev);
-}
-
-static void lan91c96_halt(struct eth_device *dev)
-{
- smc_close(dev);
-}
-
-static int lan91c96_recv(struct eth_device *dev)
-{
- return smc_rcv(dev);
-}
-
-static int lan91c96_send(struct eth_device *dev, void *packet,
- int length)
-{
- return smc_send_packet(dev, packet, length);
-}
-
-/* smc_get_ethaddr
- *
- * This checks both the environment and the ROM for an ethernet address. If
- * found, the environment takes precedence.
- */
-
-static int smc_get_ethaddr(struct bd_info *bd, struct eth_device *dev)
-{
- uchar v_mac[6];
-
- if (!eth_env_get_enetaddr("ethaddr", v_mac)) {
- /* get ROM mac value if any */
- if (!get_rom_mac(dev, v_mac)) {
- printf("\n*** ERROR: ethaddr is NOT set !!\n");
- return -1;
- }
- eth_env_set_enetaddr("ethaddr", v_mac);
- }
-
- smc_set_mac_addr(v_mac); /* use old function to update smc default */
- PRINTK("Using MAC Address %pM\n", v_mac);
- return 0;
-}
-
-/*
- * get_rom_mac()
- * Note, this has omly been tested for the OMAP730 P2.
- */
-
-static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac)
-{
- int i;
- SMC_SELECT_BANK(dev, 1);
- for (i=0; i<6; i++)
- {
- v_rom_mac[i] = SMC_inb(dev, LAN91C96_IA0 + i);
- }
- return (1);
-}
-
-/* Structure to detect the device IDs */
-struct id_type {
- u8 id;
- char *name;
-};
-static struct id_type supported_chips[] = {
- {0, ""}, /* Dummy entry to prevent id check failure */
- {9, "LAN91C110"},
- {8, "LAN91C100FD"},
- {7, "LAN91C100"},
- {5, "LAN91C95"},
- {4, "LAN91C94/96"},
- {3, "LAN91C90/92"},
-};
-/* lan91c96_detect_chip
- * See:
- * http://www.embeddedsys.com/subpages/resources/images/documents/LAN91C96_datasheet.pdf
- * page 71 - that is the closest we get to detect this device
- */
-static int lan91c96_detect_chip(struct eth_device *dev)
-{
- u8 chip_id;
- int r;
- SMC_SELECT_BANK(dev, 3);
- chip_id = (SMC_inw(dev, 0xA) & LAN91C96_REV_CHIPID) >> 4;
- SMC_SELECT_BANK(dev, 0);
- for (r = 0; r < ARRAY_SIZE(supported_chips); r++)
- if (chip_id == supported_chips[r].id)
- return r;
- return 0;
-}
-
-int lan91c96_initialize(u8 dev_num, int base_addr)
-{
- struct eth_device *dev;
- int r = 0;
-
- dev = malloc(sizeof(*dev));
- if (!dev) {
- return 0;
- }
- memset(dev, 0, sizeof(*dev));
-
- dev->iobase = base_addr;
-
- /* Try to detect chip. Will fail if not present. */
- r = lan91c96_detect_chip(dev);
- if (!r) {
- free(dev);
- return 0;
- }
- get_rom_mac(dev, dev->enetaddr);
-
- dev->init = lan91c96_init;
- dev->halt = lan91c96_halt;
- dev->send = lan91c96_send;
- dev->recv = lan91c96_recv;
- sprintf(dev->name, "%s-%hu", supported_chips[r].name, dev_num);
-
- eth_register(dev);
- return 0;
-}
diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h
deleted file mode 100644
index c76348084a33..000000000000
--- a/drivers/net/lan91c96.h
+++ /dev/null
@@ -1,616 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*------------------------------------------------------------------------
- * lan91c96.h
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Rolf Offermanns <rof@sysgo.de>
- * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- * Developed by Simple Network Magic Corporation (SNMC)
- * Copyright (C) 1996 by Erik Stahlman (ES)
- *
- * This file contains register information and access macros for
- * the LAN91C96 single chip ethernet controller. It is a modified
- * version of the smc9111.h file.
- *
- * Information contained in this file was obtained from the LAN91C96
- * manual from SMC. To get a copy, if you really want one, you can find
- * information under www.smsc.com.
- *
- * Authors
- * Erik Stahlman ( erik@vt.edu )
- * Daris A Nevil ( dnevil@snmc.com )
- *
- * History
- * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version)
- * for lan91c96
- *-------------------------------------------------------------------------
- */
-#ifndef _LAN91C96_H_
-#define _LAN91C96_H_
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <config.h>
-
-/* I want some simple types */
-
-typedef unsigned char byte;
-typedef unsigned short word;
-typedef unsigned long int dword;
-
-/*
- * DEBUGGING LEVELS
- *
- * 0 for normal operation
- * 1 for slightly more details
- * >2 for various levels of increasingly useless information
- * 2 for interrupt tracking, status flags
- * 3 for packet info
- * 4 for complete packet dumps
- */
-/*#define SMC_DEBUG 0 */
-
-/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
-
-#define SMC_IO_EXTENT 16
-
-#ifdef CONFIG_CPU_PXA25X
-
-#define SMC_IO_SHIFT 0
-
-#define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT))
-
-#define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r)))
-#define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r)))
-#define SMC_inb(edev, p) ({ \
- unsigned int __p = p; \
- unsigned int __v = SMC_inw(edev, __p & ~1); \
- if (__p & 1) __v >>= 8; \
- else __v &= 0xff; \
- __v; })
-
-#define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d)
-#define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d)
-#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
- word __w = SMC_inw(edev, (r)&~1); \
- __w &= ((r)&1) ? 0x00FF : 0xFF00; \
- __w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(edev, __w, (r)&~1); \
- })
-
-#define SMC_outsl(edev, r, b, l) ({ int __i; \
- dword *__b2; \
- __b2 = (dword *) b; \
- for (__i = 0; __i < l; __i++) { \
- SMC_outl(edev, *(__b2 + __i),\
- r); \
- } \
- })
-
-#define SMC_outsw(edev, r, b, l) ({ int __i; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- SMC_outw(edev, *(__b2 + __i),\
- r); \
- } \
- })
-
-#define SMC_insl(edev, r, b, l) ({ int __i ; \
- dword *__b2; \
- __b2 = (dword *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl(edev,\
- r); \
- SMC_inl(edev, 0); \
- }; \
- })
-
-#define SMC_insw(edev, r, b, l) ({ int __i ; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(edev,\
- r); \
- SMC_inw(edev, 0); \
- }; \
- })
-
-#define SMC_insb(edev, r, b, l) ({ int __i ; \
- byte *__b2; \
- __b2 = (byte *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inb(edev,\
- r); \
- SMC_inb(edev, 0); \
- }; \
- })
-
-#else /* if not CONFIG_CPU_PXA25X */
-
-/*
- * We have only 16 Bit PCMCIA access on Socket 0
- */
-
-#define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r))))
-#define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\
- SMC_inw(edev, r)&0xFF)
-
-#define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d)
-#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
- word __w = SMC_inw(edev, (r)&~1); \
- __w &= ((r)&1) ? 0x00FF : 0xFF00; \
- __w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(edev, __w, (r)&~1); \
- })
-#define SMC_outsw(edev, r, b, l) ({ int __i; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- SMC_outw(edev, *(__b2 + __i),\
- r); \
- } \
- })
-
-#define SMC_insw(edev, r, b, l) ({ int __i ; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(edev,\
- r); \
- SMC_inw(edev, 0); \
- }; \
- })
-
-#endif
-
-/*
- ****************************************************************************
- * Bank Select Field
- ****************************************************************************
- */
-#define LAN91C96_BANK_SELECT 14 /* Bank Select Register */
-#define LAN91C96_BANKSELECT (0x3UC << 0)
-#define BANK0 0x00
-#define BANK1 0x01
-#define BANK2 0x02
-#define BANK3 0x03
-#define BANK4 0x04
-
-/*
- ****************************************************************************
- * EEPROM Addresses.
- ****************************************************************************
- */
-#define EEPROM_MAC_OFFSET_1 0x6020
-#define EEPROM_MAC_OFFSET_2 0x6021
-#define EEPROM_MAC_OFFSET_3 0x6022
-
-/*
- ****************************************************************************
- * Bank 0 Register Map in I/O Space
- ****************************************************************************
- */
-#define LAN91C96_TCR 0 /* Transmit Control Register */
-#define LAN91C96_EPH_STATUS 2 /* EPH Status Register */
-#define LAN91C96_RCR 4 /* Receive Control Register */
-#define LAN91C96_COUNTER 6 /* Counter Register */
-#define LAN91C96_MIR 8 /* Memory Information Register */
-#define LAN91C96_MCR 10 /* Memory Configuration Register */
-
-/*
- ****************************************************************************
- * Transmit Control Register - Bank 0 - Offset 0
- ****************************************************************************
- */
-#define LAN91C96_TCR_TXENA (0x1U << 0)
-#define LAN91C96_TCR_LOOP (0x1U << 1)
-#define LAN91C96_TCR_FORCOL (0x1U << 2)
-#define LAN91C96_TCR_TXP_EN (0x1U << 3)
-#define LAN91C96_TCR_PAD_EN (0x1U << 7)
-#define LAN91C96_TCR_NOCRC (0x1U << 8)
-#define LAN91C96_TCR_MON_CSN (0x1U << 10)
-#define LAN91C96_TCR_FDUPLX (0x1U << 11)
-#define LAN91C96_TCR_STP_SQET (0x1U << 12)
-#define LAN91C96_TCR_EPH_LOOP (0x1U << 13)
-#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14)
-#define LAN91C96_TCR_FDSE (0x1U << 15)
-
-/*
- ****************************************************************************
- * EPH Status Register - Bank 0 - Offset 2
- ****************************************************************************
- */
-#define LAN91C96_EPHSR_TX_SUC (0x1U << 0)
-#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1)
-#define LAN91C96_EPHSR_MUL_COL (0x1U << 2)
-#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3)
-#define LAN91C96_EPHSR_16COL (0x1U << 4)
-#define LAN91C96_EPHSR_SQET (0x1U << 5)
-#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6)
-#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7)
-#define LAN91C96_EPHSR_WAKEUP (0x1U << 8)
-#define LAN91C96_EPHSR_LATCOL (0x1U << 9)
-#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10)
-#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11)
-#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12)
-
-#define LAN91C96_EPHSR_LINK_OK (0x1U << 14)
-#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15)
-
-#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \
- LAN91C96_EPHSR_MUL_COL | \
- LAN91C96_EPHSR_16COL | \
- LAN91C96_EPHSR_SQET | \
- LAN91C96_EPHSR_TX_DEFR | \
- LAN91C96_EPHSR_LATCOL | \
- LAN91C96_EPHSR_LOST_CARR | \
- LAN91C96_EPHSR_EXC_DEF | \
- LAN91C96_EPHSR_LINK_OK | \
- LAN91C96_EPHSR_TX_UNRN)
-
-/*
- ****************************************************************************
- * Receive Control Register - Bank 0 - Offset 4
- ****************************************************************************
- */
-#define LAN91C96_RCR_RX_ABORT (0x1U << 0)
-#define LAN91C96_RCR_PRMS (0x1U << 1)
-#define LAN91C96_RCR_ALMUL (0x1U << 2)
-#define LAN91C96_RCR_RXEN (0x1U << 8)
-#define LAN91C96_RCR_STRIP_CRC (0x1U << 9)
-#define LAN91C96_RCR_FILT_CAR (0x1U << 14)
-#define LAN91C96_RCR_SOFT_RST (0x1U << 15)
-
-/*
- ****************************************************************************
- * Counter Register - Bank 0 - Offset 6
- ****************************************************************************
- */
-#define LAN91C96_ECR_SNGL_COL (0xFU << 0)
-#define LAN91C96_ECR_MULT_COL (0xFU << 5)
-#define LAN91C96_ECR_DEF_TX (0xFU << 8)
-#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12)
-
-/*
- ****************************************************************************
- * Memory Information Register - Bank 0 - OFfset 8
- ****************************************************************************
- */
-#define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */
-
-/*
- ****************************************************************************
- * Memory Configuration Register - Bank 0 - Offset 10
- ****************************************************************************
- */
-#define LAN91C96_MCR_MEM_RES (0xFFU << 0)
-#define LAN91C96_MCR_MEM_MULT (0x3U << 9)
-#define LAN91C96_MCR_HIGH_ID (0x3U << 12)
-
-#define LAN91C96_MCR_TRANSMIT_PAGES 0x6
-
-/*
- ****************************************************************************
- * Bank 1 Register Map in I/O Space
- ****************************************************************************
- */
-#define LAN91C96_CONFIG 0 /* Configuration Register */
-#define LAN91C96_BASE 2 /* Base Address Register */
-#define LAN91C96_IA0 4 /* Individual Address Register - 0 */
-#define LAN91C96_IA1 5 /* Individual Address Register - 1 */
-#define LAN91C96_IA2 6 /* Individual Address Register - 2 */
-#define LAN91C96_IA3 7 /* Individual Address Register - 3 */
-#define LAN91C96_IA4 8 /* Individual Address Register - 4 */
-#define LAN91C96_IA5 9 /* Individual Address Register - 5 */
-#define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */
-#define LAN91C96_CONTROL 12 /* Control Register */
-
-/*
- ****************************************************************************
- * Configuration Register - Bank 1 - Offset 0
- ****************************************************************************
- */
-#define LAN91C96_CR_INT_SEL0 (0x1U << 1)
-#define LAN91C96_CR_INT_SEL1 (0x1U << 2)
-#define LAN91C96_CR_RES (0x3U << 3)
-#define LAN91C96_CR_DIS_LINK (0x1U << 6)
-#define LAN91C96_CR_16BIT (0x1U << 7)
-#define LAN91C96_CR_AUI_SELECT (0x1U << 8)
-#define LAN91C96_CR_SET_SQLCH (0x1U << 9)
-#define LAN91C96_CR_FULL_STEP (0x1U << 10)
-#define LAN91C96_CR_NO_WAIT (0x1U << 12)
-
-/*
- ****************************************************************************
- * Base Address Register - Bank 1 - Offset 2
- ****************************************************************************
- */
-#define LAN91C96_BAR_RA_BITS (0x27U << 0)
-#define LAN91C96_BAR_ROM_SIZE (0x1U << 6)
-#define LAN91C96_BAR_A_BITS (0xFFU << 8)
-
-/*
- ****************************************************************************
- * Control Register - Bank 1 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_CTR_STORE (0x1U << 0)
-#define LAN91C96_CTR_RELOAD (0x1U << 1)
-#define LAN91C96_CTR_EEPROM (0x1U << 2)
-#define LAN91C96_CTR_TE_ENABLE (0x1U << 5)
-#define LAN91C96_CTR_CR_ENABLE (0x1U << 6)
-#define LAN91C96_CTR_LE_ENABLE (0x1U << 7)
-#define LAN91C96_CTR_BIT_8 (0x1U << 8)
-#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
-#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12)
-#define LAN91C96_CTR_PWRDN (0x1U << 13)
-#define LAN91C96_CTR_RCV_BAD (0x1U << 14)
-
-/*
- ****************************************************************************
- * Bank 2 Register Map in I/O Space
- ****************************************************************************
- */
-#define LAN91C96_MMU 0 /* MMU Command Register */
-#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */
-#define LAN91C96_PNR 2 /* Packet Number Register */
-#define LAN91C96_ARR 3 /* Allocation Result Register */
-#define LAN91C96_FIFO 4 /* FIFO Ports Register */
-#define LAN91C96_POINTER 6 /* Pointer Register */
-#define LAN91C96_DATA_HIGH 8 /* Data High Register */
-#define LAN91C96_DATA_LOW 10 /* Data Low Register */
-#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */
-#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */
-#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */
-
-/*
- ****************************************************************************
- * MMU Command Register - Bank 2 - Offset 0
- ****************************************************************************
- */
-#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0)
-#define LAN91C96_MMUCR_N1 (0x1U << 1)
-#define LAN91C96_MMUCR_N2 (0x1U << 2)
-#define LAN91C96_MMUCR_COMMAND (0xFU << 4)
-#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */
-#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */
-#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */
-#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */
-#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */
-#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */
-#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */
-#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */
-
-/*
- ****************************************************************************
- * Auto Tx Start Register - Bank 2 - Offset 1
- ****************************************************************************
- */
-#define LAN91C96_AUTOTX (0xFFU << 0)
-
-/*
- ****************************************************************************
- * Packet Number Register - Bank 2 - Offset 2
- ****************************************************************************
- */
-#define LAN91C96_PNR_TX (0x1FU << 0)
-
-/*
- ****************************************************************************
- * Allocation Result Register - Bank 2 - Offset 3
- ****************************************************************************
- */
-#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0)
-#define LAN91C96_ARR_FAILED (0x1U << 7)
-
-/*
- ****************************************************************************
- * FIFO Ports Register - Bank 2 - Offset 4
- ****************************************************************************
- */
-#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0)
-#define LAN91C96_FIFO_TEMPTY (0x1U << 7)
-#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8)
-#define LAN91C96_FIFO_RXEMPTY (0x1U << 15)
-
-/*
- ****************************************************************************
- * Pointer Register - Bank 2 - Offset 6
- ****************************************************************************
- */
-#define LAN91C96_PTR_LOW (0xFFU << 0)
-#define LAN91C96_PTR_HIGH (0x7U << 8)
-#define LAN91C96_PTR_AUTO_TX (0x1U << 11)
-#define LAN91C96_PTR_ETEN (0x1U << 12)
-#define LAN91C96_PTR_READ (0x1U << 13)
-#define LAN91C96_PTR_AUTO_INCR (0x1U << 14)
-#define LAN91C96_PTR_RCV (0x1U << 15)
-
-#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \
- LAN91C96_PTR_AUTO_INCR | \
- LAN91C96_PTR_READ)
-
-/*
- ****************************************************************************
- * Data Register - Bank 2 - Offset 8
- ****************************************************************************
- */
-#define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */
-#define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */
-
-/*
- ****************************************************************************
- * Interrupt Status Register - Bank 2 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_IST_RCV_INT (0x1U << 0)
-#define LAN91C96_IST_TX_INT (0x1U << 1)
-#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
-#define LAN91C96_IST_ALLOC_INT (0x1U << 3)
-#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4)
-#define LAN91C96_IST_EPH_INT (0x1U << 5)
-#define LAN91C96_IST_ERCV_INT (0x1U << 6)
-#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7)
-
-/*
- ****************************************************************************
- * Interrupt Acknowledge Register - Bank 2 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_ACK_TX_INT (0x1U << 1)
-#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
-#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4)
-#define LAN91C96_ACK_ERCV_INT (0x1U << 6)
-
-/*
- ****************************************************************************
- * Interrupt Mask Register - Bank 2 - Offset 13
- ****************************************************************************
- */
-#define LAN91C96_MSK_RCV_INT (0x1U << 0)
-#define LAN91C96_MSK_TX_INT (0x1U << 1)
-#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
-#define LAN91C96_MSK_ALLOC_INT (0x1U << 3)
-#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4)
-#define LAN91C96_MSK_EPH_INT (0x1U << 5)
-#define LAN91C96_MSK_ERCV_INT (0x1U << 6)
-#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7)
-
-/*
- ****************************************************************************
- * Bank 3 Register Map in I/O Space
- **************************************************************************
- */
-#define LAN91C96_MGMT_MDO (0x1U << 0)
-#define LAN91C96_MGMT_MDI (0x1U << 1)
-#define LAN91C96_MGMT_MCLK (0x1U << 2)
-#define LAN91C96_MGMT_MDOE (0x1U << 3)
-#define LAN91C96_MGMT_LOW_ID (0x3U << 4)
-#define LAN91C96_MGMT_IOS0 (0x1U << 8)
-#define LAN91C96_MGMT_IOS1 (0x1U << 9)
-#define LAN91C96_MGMT_IOS2 (0x1U << 10)
-#define LAN91C96_MGMT_nXNDEC (0x1U << 11)
-#define LAN91C96_MGMT_HIGH_ID (0x3U << 12)
-
-/*
- ****************************************************************************
- * Revision Register - Bank 3 - Offset 10
- ****************************************************************************
- */
-#define LAN91C96_REV_REVID (0xFU << 0)
-#define LAN91C96_REV_CHIPID (0xFU << 4)
-
-/*
- ****************************************************************************
- * Early RCV Register - Bank 3 - Offset 12
- ****************************************************************************
- */
-#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0)
-#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7)
-
-/*
- ****************************************************************************
- * PCMCIA Configuration Registers
- ****************************************************************************
- */
-#define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */
-#define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */
-
-/*
- ****************************************************************************
- * PCMCIA Ethernet Configuration Option Register (ECOR)
- ****************************************************************************
- */
-#define LAN91C96_ECOR_ENABLE (0x1U << 0)
-#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2)
-#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6)
-#define LAN91C96_ECOR_SRESET (0x1U << 7)
-
-/*
- ****************************************************************************
- * PCMCIA Ethernet Configuration and Status Register (ECSR)
- ****************************************************************************
- */
-#define LAN91C96_ECSR_INTR (0x1U << 1)
-#define LAN91C96_ECSR_PWRDWN (0x1U << 2)
-#define LAN91C96_ECSR_IOIS8 (0x1U << 5)
-
-/*
- ****************************************************************************
- * Receive Frame Status Word - See page 38 of the LAN91C96 specification.
- ****************************************************************************
- */
-#define LAN91C96_TOO_SHORT (0x1U << 10)
-#define LAN91C96_TOO_LONG (0x1U << 11)
-#define LAN91C96_ODD_FRM (0x1U << 12)
-#define LAN91C96_BAD_CRC (0x1U << 13)
-#define LAN91C96_BROD_CAST (0x1U << 14)
-#define LAN91C96_ALGN_ERR (0x1U << 15)
-
-#define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR)
-
-/*
- ****************************************************************************
- * Default MAC Address
- ****************************************************************************
- */
-#define MAC_DEF_HI 0x0800
-#define MAC_DEF_MED 0x3333
-#define MAC_DEF_LO 0x0100
-
-/*
- ****************************************************************************
- * Default I/O Signature - 0x33
- ****************************************************************************
- */
-#define LAN91C96_LOW_SIGNATURE (0x33U << 0)
-#define LAN91C96_HIGH_SIGNATURE (0x33U << 8)
-#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
-
-#define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */
-#define ETHERNET_MAX_LENGTH 1514
-
-
-/*-------------------------------------------------------------------------
- * I define some macros to make it easier to do somewhat common
- * or slightly complicated, repeated tasks.
- *-------------------------------------------------------------------------
- */
-
-/* select a register bank, 0 to 3 */
-
-#define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); }
-
-/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(edev, x) {\
- unsigned char mask;\
- SMC_SELECT_BANK(edev, 2);\
- mask = SMC_inb(edev, LAN91C96_INT_MASK);\
- mask |= (x);\
- SMC_outb(edev, mask, LAN91C96_INT_MASK); \
-}
-
-/* this disables an interrupt from the interrupt mask register */
-
-#define SMC_DISABLE_INT(edev, x) {\
- unsigned char mask;\
- SMC_SELECT_BANK(edev, 2);\
- mask = SMC_inb(edev, LAN91C96_INT_MASK);\
- mask &= ~(x);\
- SMC_outb(edev, mask, LAN91C96_INT_MASK); \
-}
-
-/*----------------------------------------------------------------------
- * Define the interrupts that I want to receive from the card
- *
- * I want:
- * LAN91C96_IST_EPH_INT, for nasty errors
- * LAN91C96_IST_RCV_INT, for happy received packets
- * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
- *-------------------------------------------------------------------------
- */
-#define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
-
-#endif /* _LAN91C96_H_ */
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 07/10] net: Remove natsemi driver
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
` (4 preceding siblings ...)
2022-03-31 17:46 ` [PATCH 06/10] net: Remove lan91c96 driver Tom Rini
@ 2022-03-31 17:46 ` Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 08/10] net: Remove ns8382x driver Tom Rini
` (3 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
This driver is not enabled by any board and not converted to DM_ETH.
Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/net/Makefile | 1 -
drivers/net/natsemi.c | 883 ------------------------------------------
2 files changed, 884 deletions(-)
delete mode 100644 drivers/net/natsemi.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index be3264e04133..f902f0d06c26 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -64,7 +64,6 @@ obj-$(CONFIG_MVGBE) += mvgbe.o
obj-$(CONFIG_MVMDIO) += mvmdio.o
obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
-obj-$(CONFIG_NATSEMI) += natsemi.o
obj-$(CONFIG_NETCONSOLE) += netconsole.o
obj-$(CONFIG_NET_OCTEONTX) += octeontx/
obj-$(CONFIG_NET_OCTEONTX2) += octeontx2/
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
deleted file mode 100644
index bfd8cc396b98..000000000000
--- a/drivers/net/natsemi.c
+++ /dev/null
@@ -1,883 +0,0 @@
-/*
- natsemi.c: A U-Boot driver for the NatSemi DP8381x series.
- Author: Mark A. Rakes (mark_rakes@vivato.net)
-
- Adapted from an Etherboot driver written by:
-
- Copyright (C) 2001 Entity Cyber, Inc.
-
- This development of this Etherboot driver was funded by
-
- Sicom Systems: http://www.sicompos.com/
-
- Author: Marty Connor (mdc@thinguin.org)
- Adapted from a Linux driver which was written by Donald Becker
-
- This software may be used and distributed according to the terms
- of the GNU Public License (GPL), incorporated herein by reference.
-
- Original Copyright Notice:
-
- Written/copyright 1999-2001 by Donald Becker.
-
- This software may be used and distributed according to the terms of
- the GNU General Public License (GPL), incorporated herein by reference.
- Drivers based on or derived from this code fall under the GPL and must
- retain the authorship, copyright and license notice. This file is not
- a complete program and may only be used when the entire operating
- system is licensed under the GPL. License for under other terms may be
- available. Contact the original author for details.
-
- The original author may be reached as becker@scyld.com, or at
- Scyld Computing Corporation
- 410 Severn Ave., Suite 210
- Annapolis MD 21403
-
- Support information and updates available at
- http://www.scyld.com/network/netsemi.html
-
- References:
- http://www.scyld.com/expert/100mbps.html
- http://www.scyld.com/expert/NWay.html
- Datasheet is available from:
- http://www.national.com/pf/DP/DP83815.html
-*/
-
-/* Revision History
- * October 2002 mar 1.0
- * Initial U-Boot Release. Tested with Netgear FA311 board
- * and dp83815 chipset on custom board
-*/
-
-/* Includes */
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <linux/delay.h>
-
-/* defines */
-#define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
-
-#define DSIZE 0x00000FFF
-#define CRC_SIZE 4
-#define TOUT_LOOP 500000
-#define TX_BUF_SIZE 1536
-#define RX_BUF_SIZE 1536
-#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
-
-/* Offsets to the device registers.
- Unlike software-only systems, device drivers interact with complex hardware.
- It's not useful to define symbolic names for every register bit in the
- device. */
-enum register_offsets {
- ChipCmd = 0x00,
- ChipConfig = 0x04,
- EECtrl = 0x08,
- IntrMask = 0x14,
- IntrEnable = 0x18,
- TxRingPtr = 0x20,
- TxConfig = 0x24,
- RxRingPtr = 0x30,
- RxConfig = 0x34,
- ClkRun = 0x3C,
- RxFilterAddr = 0x48,
- RxFilterData = 0x4C,
- SiliconRev = 0x58,
- PCIPM = 0x44,
- BasicControl = 0x80,
- BasicStatus = 0x84,
- /* These are from the spec, around page 78... on a separate table. */
- PGSEL = 0xCC,
- PMDCSR = 0xE4,
- TSTDAT = 0xFC,
- DSPCFG = 0xF4,
- SDCFG = 0x8C
-};
-
-/* Bit in ChipCmd. */
-enum ChipCmdBits {
- ChipReset = 0x100,
- RxReset = 0x20,
- TxReset = 0x10,
- RxOff = 0x08,
- RxOn = 0x04,
- TxOff = 0x02,
- TxOn = 0x01
-};
-
-enum ChipConfigBits {
- LinkSts = 0x80000000,
- HundSpeed = 0x40000000,
- FullDuplex = 0x20000000,
- TenPolarity = 0x10000000,
- AnegDone = 0x08000000,
- AnegEnBothBoth = 0x0000E000,
- AnegDis100Full = 0x0000C000,
- AnegEn100Both = 0x0000A000,
- AnegDis100Half = 0x00008000,
- AnegEnBothHalf = 0x00006000,
- AnegDis10Full = 0x00004000,
- AnegEn10Both = 0x00002000,
- DuplexMask = 0x00008000,
- SpeedMask = 0x00004000,
- AnegMask = 0x00002000,
- AnegDis10Half = 0x00000000,
- ExtPhy = 0x00001000,
- PhyRst = 0x00000400,
- PhyDis = 0x00000200,
- BootRomDisable = 0x00000004,
- BEMode = 0x00000001,
-};
-
-enum TxConfig_bits {
- TxDrthMask = 0x3f,
- TxFlthMask = 0x3f00,
- TxMxdmaMask = 0x700000,
- TxMxdma_512 = 0x0,
- TxMxdma_4 = 0x100000,
- TxMxdma_8 = 0x200000,
- TxMxdma_16 = 0x300000,
- TxMxdma_32 = 0x400000,
- TxMxdma_64 = 0x500000,
- TxMxdma_128 = 0x600000,
- TxMxdma_256 = 0x700000,
- TxCollRetry = 0x800000,
- TxAutoPad = 0x10000000,
- TxMacLoop = 0x20000000,
- TxHeartIgn = 0x40000000,
- TxCarrierIgn = 0x80000000
-};
-
-enum RxConfig_bits {
- RxDrthMask = 0x3e,
- RxMxdmaMask = 0x700000,
- RxMxdma_512 = 0x0,
- RxMxdma_4 = 0x100000,
- RxMxdma_8 = 0x200000,
- RxMxdma_16 = 0x300000,
- RxMxdma_32 = 0x400000,
- RxMxdma_64 = 0x500000,
- RxMxdma_128 = 0x600000,
- RxMxdma_256 = 0x700000,
- RxAcceptLong = 0x8000000,
- RxAcceptTx = 0x10000000,
- RxAcceptRunt = 0x40000000,
- RxAcceptErr = 0x80000000
-};
-
-/* Bits in the RxMode register. */
-enum rx_mode_bits {
- AcceptErr = 0x20,
- AcceptRunt = 0x10,
- AcceptBroadcast = 0xC0000000,
- AcceptMulticast = 0x00200000,
- AcceptAllMulticast = 0x20000000,
- AcceptAllPhys = 0x10000000,
- AcceptMyPhys = 0x08000000
-};
-
-typedef struct _BufferDesc {
- u32 link;
- vu_long cmdsts;
- u32 bufptr;
- u32 software_use;
-} BufferDesc;
-
-/* Bits in network_desc.status */
-enum desc_status_bits {
- DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
- DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
- DescSizeMask = 0xfff,
-
- DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
- DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
- DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
- DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
-
- DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
- DescRxDest = 0x01800000, DescRxLong = 0x00400000,
- DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
- DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
- DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
-};
-
-/* Globals */
-#ifdef NATSEMI_DEBUG
-static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */
-#endif
-static u32 SavedClkRun;
-static unsigned int cur_rx;
-static unsigned int advertising;
-static unsigned int rx_config;
-static unsigned int tx_config;
-
-/* Note: transmit and receive buffers and descriptors must be
- longword aligned */
-static BufferDesc txd __attribute__ ((aligned(4)));
-static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4)));
-
-static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4)));
-static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
- __attribute__ ((aligned(4)));
-
-/* Function Prototypes */
-#if 0
-static void write_eeprom(struct eth_device *dev, long addr, int location,
- short value);
-#endif
-static int read_eeprom(struct eth_device *dev, long addr, int location);
-static int mdio_read(struct eth_device *dev, int phy_id, int location);
-static int natsemi_init(struct eth_device *dev, struct bd_info * bis);
-static void natsemi_reset(struct eth_device *dev);
-static void natsemi_init_rxfilter(struct eth_device *dev);
-static void natsemi_init_txd(struct eth_device *dev);
-static void natsemi_init_rxd(struct eth_device *dev);
-static void natsemi_set_rx_mode(struct eth_device *dev);
-static void natsemi_check_duplex(struct eth_device *dev);
-static int natsemi_send(struct eth_device *dev, void *packet, int length);
-static int natsemi_poll(struct eth_device *dev);
-static void natsemi_disable(struct eth_device *dev);
-
-static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815},
- {}
-};
-
-#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
-
-static inline int
-INW(struct eth_device *dev, u_long addr)
-{
- return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
-}
-
-static int
-INL(struct eth_device *dev, u_long addr)
-{
- return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
-}
-
-static inline void
-OUTW(struct eth_device *dev, int command, u_long addr)
-{
- *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
-}
-
-static inline void
-OUTL(struct eth_device *dev, int command, u_long addr)
-{
- *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
-}
-
-/*
- * Function: natsemi_initialize
- *
- * Description: Retrieves the MAC address of the card, and sets up some
- * globals required by other routines, and initializes the NIC, making it
- * ready to send and receive packets.
- *
- * Side effects:
- * leaves the natsemi initialized, and ready to receive packets.
- *
- * Returns: struct eth_device *: pointer to NIC data structure
- */
-
-int
-natsemi_initialize(struct bd_info * bis)
-{
- pci_dev_t devno;
- int card_number = 0;
- struct eth_device *dev;
- u32 iobase, status, chip_config;
- int i, idx = 0;
- int prev_eedata;
- u32 tmp;
-
- while (1) {
- /* Find PCI device(s) */
- if ((devno = pci_find_devices(supported, idx++)) < 0) {
- break;
- }
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
- iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */
-
- pci_write_config_dword(devno, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Check if I/O accesses and Bus Mastering are enabled. */
- pci_read_config_dword(devno, PCI_COMMAND, &status);
- if (!(status & PCI_COMMAND_MEMORY)) {
- printf("Error: Can not enable MEM access.\n");
- continue;
- } else if (!(status & PCI_COMMAND_MASTER)) {
- printf("Error: Can not enable Bus Mastering.\n");
- continue;
- }
-
- dev = (struct eth_device *) malloc(sizeof *dev);
- if (!dev) {
- printf("natsemi: Can not allocate memory\n");
- break;
- }
- memset(dev, 0, sizeof(*dev));
-
- sprintf(dev->name, "dp83815#%d", card_number);
- dev->iobase = bus_to_phys(iobase);
-#ifdef NATSEMI_DEBUG
- printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase);
-#endif
- dev->priv = (void *) devno;
- dev->init = natsemi_init;
- dev->halt = natsemi_disable;
- dev->send = natsemi_send;
- dev->recv = natsemi_poll;
-
- eth_register(dev);
-
- card_number++;
-
- /* Set the latency timer for value. */
- pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
-
- udelay(10 * 1000);
-
- /* natsemi has a non-standard PM control register
- * in PCI config space. Some boards apparently need
- * to be brought to D0 in this manner. */
- pci_read_config_dword(devno, PCIPM, &tmp);
- if (tmp & (0x03 | 0x100)) {
- /* D0 state, disable PME assertion */
- u32 newtmp = tmp & ~(0x03 | 0x100);
- pci_write_config_dword(devno, PCIPM, newtmp);
- }
-
- printf("natsemi: EEPROM contents:\n");
- for (i = 0; i <= EEPROM_SIZE; i++) {
- short eedata = read_eeprom(dev, EECtrl, i);
- printf(" %04hx", eedata);
- }
- printf("\n");
-
- /* get MAC address */
- prev_eedata = read_eeprom(dev, EECtrl, 6);
- for (i = 0; i < 3; i++) {
- int eedata = read_eeprom(dev, EECtrl, i + 7);
- dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15);
- dev->enetaddr[i*2+1] = eedata >> 7;
- prev_eedata = eedata;
- }
-
- /* Reset the chip to erase any previous misconfiguration. */
- OUTL(dev, ChipReset, ChipCmd);
-
- advertising = mdio_read(dev, 1, 4);
- chip_config = INL(dev, ChipConfig);
-#ifdef NATSEMI_DEBUG
- printf("%s: Transceiver status %#08X advertising %#08X\n",
- dev->name, (int) INL(dev, BasicStatus), advertising);
- printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n",
- dev->name, chip_config & AnegMask ? "enabled, advertise" :
- "disabled, force", chip_config & SpeedMask ? "0" : "",
- chip_config & DuplexMask ? "full" : "half");
-#endif
- chip_config |= AnegEnBothBoth;
-#ifdef NATSEMI_DEBUG
- printf("%s: changed to autoneg. %s 10%s %s duplex.\n",
- dev->name, chip_config & AnegMask ? "enabled, advertise" :
- "disabled, force", chip_config & SpeedMask ? "0" : "",
- chip_config & DuplexMask ? "full" : "half");
-#endif
- /*write new autoneg bits, reset phy*/
- OUTL(dev, (chip_config | PhyRst), ChipConfig);
- /*un-reset phy*/
- OUTL(dev, chip_config, ChipConfig);
-
- /* Disable PME:
- * The PME bit is initialized from the EEPROM contents.
- * PCI cards probably have PME disabled, but motherboard
- * implementations may have PME set to enable WakeOnLan.
- * With PME set the chip will scan incoming packets but
- * nothing will be written to memory. */
- SavedClkRun = INL(dev, ClkRun);
- OUTL(dev, SavedClkRun & ~0x100, ClkRun);
- }
- return card_number;
-}
-
-/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
- The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
-
-/* Delay between EEPROM clock transitions.
- No extra delay is needed with 33MHz PCI, but future 66MHz
- access may need a delay. */
-#define eeprom_delay(ee_addr) INL(dev, ee_addr)
-
-enum EEPROM_Ctrl_Bits {
- EE_ShiftClk = 0x04,
- EE_DataIn = 0x01,
- EE_ChipSelect = 0x08,
- EE_DataOut = 0x02
-};
-
-#define EE_Write0 (EE_ChipSelect)
-#define EE_Write1 (EE_ChipSelect | EE_DataIn)
-/* The EEPROM commands include the alway-set leading bit. */
-enum EEPROM_Cmds {
- EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6),
- EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6),
-};
-
-#if 0
-static void
-write_eeprom(struct eth_device *dev, long addr, int location, short value)
-{
- int i;
- int ee_addr = (typeof(ee_addr))addr;
- short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/
- short write_cmd = location | EE_WriteCmd;
-
-#ifdef NATSEMI_DEBUG
- printf("write_eeprom: %08x, %04hx, %04hx\n",
- dev->iobase + ee_addr, write_cmd, value);
-#endif
- /* Shift the write enable command bits out. */
- for (i = 9; i >= 0; i--) {
- short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
- OUTL(dev, cmdval, ee_addr);
- eeprom_delay(ee_addr);
- OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- }
-
- OUTL(dev, 0, ee_addr); /*bring chip select low*/
- OUTL(dev, EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
-
- /* Shift the write command bits out. */
- for (i = 9; i >= 0; i--) {
- short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
- OUTL(dev, cmdval, ee_addr);
- eeprom_delay(ee_addr);
- OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- }
-
- for (i = 0; i < 16; i++) {
- short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0;
- OUTL(dev, cmdval, ee_addr);
- eeprom_delay(ee_addr);
- OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- }
-
- OUTL(dev, 0, ee_addr); /*bring chip select low*/
- OUTL(dev, EE_ShiftClk, ee_addr);
- for (i = 0; i < 200000; i++) {
- OUTL(dev, EE_Write0, ee_addr); /*poll for done*/
- if (INL(dev, ee_addr) & EE_DataOut) {
- break; /*finished*/
- }
- }
- eeprom_delay(ee_addr);
-
- /* Terminate the EEPROM access. */
- OUTL(dev, EE_Write0, ee_addr);
- OUTL(dev, 0, ee_addr);
- return;
-}
-#endif
-
-static int
-read_eeprom(struct eth_device *dev, long addr, int location)
-{
- int i;
- int retval = 0;
- int ee_addr = (typeof(ee_addr))addr;
- int read_cmd = location | EE_ReadCmd;
-
- OUTL(dev, EE_Write0, ee_addr);
-
- /* Shift the read command bits out. */
- for (i = 10; i >= 0; i--) {
- short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
- OUTL(dev, dataval, ee_addr);
- eeprom_delay(ee_addr);
- OUTL(dev, dataval | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- }
- OUTL(dev, EE_ChipSelect, ee_addr);
- eeprom_delay(ee_addr);
-
- for (i = 0; i < 16; i++) {
- OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr);
- eeprom_delay(ee_addr);
- retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0;
- OUTL(dev, EE_ChipSelect, ee_addr);
- eeprom_delay(ee_addr);
- }
-
- /* Terminate the EEPROM access. */
- OUTL(dev, EE_Write0, ee_addr);
- OUTL(dev, 0, ee_addr);
-#ifdef NATSEMI_DEBUG
- if (natsemi_debug)
- printf("read_eeprom: %08x, %08x, retval %08x\n",
- dev->iobase + ee_addr, read_cmd, retval);
-#endif
- return retval;
-}
-
-/* MII transceiver control section.
- The 83815 series has an internal transceiver, and we present the
- management registers as if they were MII connected. */
-
-static int
-mdio_read(struct eth_device *dev, int phy_id, int location)
-{
- if (phy_id == 1 && location < 32)
- return INL(dev, BasicControl+(location<<2))&0xffff;
- else
- return 0xffff;
-}
-
-/* Function: natsemi_init
- *
- * Description: resets the ethernet controller chip and configures
- * registers and data structures required for sending and receiving packets.
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * returns: int.
- */
-
-static int
-natsemi_init(struct eth_device *dev, struct bd_info * bis)
-{
-
- natsemi_reset(dev);
-
- /* Disable PME:
- * The PME bit is initialized from the EEPROM contents.
- * PCI cards probably have PME disabled, but motherboard
- * implementations may have PME set to enable WakeOnLan.
- * With PME set the chip will scan incoming packets but
- * nothing will be written to memory. */
- OUTL(dev, SavedClkRun & ~0x100, ClkRun);
-
- natsemi_init_rxfilter(dev);
- natsemi_init_txd(dev);
- natsemi_init_rxd(dev);
-
- /* Configure the PCI bus bursts and FIFO thresholds. */
- tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
- rx_config = RxMxdma_256 | 0x20;
-
-#ifdef NATSEMI_DEBUG
- printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
- printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
-#endif
- OUTL(dev, tx_config, TxConfig);
- OUTL(dev, rx_config, RxConfig);
-
- natsemi_check_duplex(dev);
- natsemi_set_rx_mode(dev);
-
- OUTL(dev, (RxOn | TxOn), ChipCmd);
- return 1;
-}
-
-/*
- * Function: natsemi_reset
- *
- * Description: soft resets the controller chip
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: void.
- */
-static void
-natsemi_reset(struct eth_device *dev)
-{
- OUTL(dev, ChipReset, ChipCmd);
-
- /* On page 78 of the spec, they recommend some settings for "optimum
- performance" to be done in sequence. These settings optimize some
- of the 100Mbit autodetection circuitry. Also, we only want to do
- this for rev C of the chip. */
- if (INL(dev, SiliconRev) == 0x302) {
- OUTW(dev, 0x0001, PGSEL);
- OUTW(dev, 0x189C, PMDCSR);
- OUTW(dev, 0x0000, TSTDAT);
- OUTW(dev, 0x5040, DSPCFG);
- OUTW(dev, 0x008C, SDCFG);
- }
- /* Disable interrupts using the mask. */
- OUTL(dev, 0, IntrMask);
- OUTL(dev, 0, IntrEnable);
-}
-
-/* Function: natsemi_init_rxfilter
- *
- * Description: sets receive filter address to our MAC address
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * returns: void.
- */
-
-static void
-natsemi_init_rxfilter(struct eth_device *dev)
-{
- int i;
-
- for (i = 0; i < ETH_ALEN; i += 2) {
- OUTL(dev, i, RxFilterAddr);
- OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
- RxFilterData);
- }
-}
-
-/*
- * Function: natsemi_init_txd
- *
- * Description: initializes the Tx descriptor
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * returns: void.
- */
-
-static void
-natsemi_init_txd(struct eth_device *dev)
-{
- txd.link = (u32) 0;
- txd.cmdsts = (u32) 0;
- txd.bufptr = (u32) & txb[0];
-
- /* load Transmit Descriptor Register */
- OUTL(dev, (u32) & txd, TxRingPtr);
-#ifdef NATSEMI_DEBUG
- printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n",
- INL(dev, TxRingPtr));
-#endif
-}
-
-/* Function: natsemi_init_rxd
- *
- * Description: initializes the Rx descriptor ring
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: void.
- */
-
-static void
-natsemi_init_rxd(struct eth_device *dev)
-{
- int i;
-
- cur_rx = 0;
-
- /* init RX descriptor */
- for (i = 0; i < NUM_RX_DESC; i++) {
- rxd[i].link =
- cpu_to_le32((i + 1 <
- NUM_RX_DESC) ? (u32) & rxd[i +
- 1] : (u32) &
- rxd[0]);
- rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
- rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
-#ifdef NATSEMI_DEBUG
- printf
- ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n",
- i, &rxd[i], le32_to_cpu(rxd[i].link),
- rxd[i].cmdsts, rxd[i].bufptr);
-#endif
- }
-
- /* load Receive Descriptor Register */
- OUTL(dev, (u32) & rxd[0], RxRingPtr);
-
-#ifdef NATSEMI_DEBUG
- printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n",
- INL(dev, RxRingPtr));
-#endif
-}
-
-/* Function: natsemi_set_rx_mode
- *
- * Description:
- * sets the receive mode to accept all broadcast packets and packets
- * with our MAC address, and reject all multicast packets.
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: void.
- */
-
-static void
-natsemi_set_rx_mode(struct eth_device *dev)
-{
- u32 rx_mode = AcceptBroadcast | AcceptMyPhys;
-
- OUTL(dev, rx_mode, RxFilterAddr);
-}
-
-static void
-natsemi_check_duplex(struct eth_device *dev)
-{
- int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0;
-
-#ifdef NATSEMI_DEBUG
- printf("%s: Setting %s-duplex based on negotiated link"
- " capability.\n", dev->name, duplex ? "full" : "half");
-#endif
- if (duplex) {
- rx_config |= RxAcceptTx;
- tx_config |= (TxCarrierIgn | TxHeartIgn);
- } else {
- rx_config &= ~RxAcceptTx;
- tx_config &= ~(TxCarrierIgn | TxHeartIgn);
- }
- OUTL(dev, tx_config, TxConfig);
- OUTL(dev, rx_config, RxConfig);
-}
-
-/* Function: natsemi_send
- *
- * Description: transmits a packet and waits for completion or timeout.
- *
- * Returns: void. */
-static int natsemi_send(struct eth_device *dev, void *packet, int length)
-{
- u32 i, status = 0;
- u32 tx_status = 0;
- u32 *tx_ptr = &tx_status;
- vu_long *res = (vu_long *)tx_ptr;
-
- /* Stop the transmitter */
- OUTL(dev, TxOff, ChipCmd);
-
-#ifdef NATSEMI_DEBUG
- if (natsemi_debug)
- printf("natsemi_send: sending %d bytes\n", (int) length);
-#endif
-
- /* set the transmit buffer descriptor and enable Transmit State Machine */
- txd.link = cpu_to_le32(0);
- txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet));
- txd.cmdsts = cpu_to_le32(DescOwn | length);
-
- /* load Transmit Descriptor Register */
- OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
-#ifdef NATSEMI_DEBUG
- if (natsemi_debug)
- printf("natsemi_send: TX descriptor register loaded with: %#08X\n",
- INL(dev, TxRingPtr));
-#endif
- /* restart the transmitter */
- OUTL(dev, TxOn, ChipCmd);
-
- for (i = 0;
- (*res = le32_to_cpu(txd.cmdsts)) & DescOwn;
- i++) {
- if (i >= TOUT_LOOP) {
- printf
- ("%s: tx error buffer not ready: txd.cmdsts == %#X\n",
- dev->name, tx_status);
- goto Done;
- }
- }
-
- if (!(tx_status & DescPktOK)) {
- printf("natsemi_send: Transmit error, Tx status %X.\n",
- tx_status);
- goto Done;
- }
-
- status = 1;
- Done:
- return status;
-}
-
-/* Function: natsemi_poll
- *
- * Description: checks for a received packet and returns it if found.
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: 1 if packet was received.
- * 0 if no packet was received.
- *
- * Side effects:
- * Returns (copies) the packet to the array dev->packet.
- * Returns the length of the packet.
- */
-
-static int
-natsemi_poll(struct eth_device *dev)
-{
- int retstat = 0;
- int length = 0;
- u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
-
- if (!(rx_status & (u32) DescOwn))
- return retstat;
-#ifdef NATSEMI_DEBUG
- if (natsemi_debug)
- printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n",
- cur_rx, rx_status);
-#endif
- length = (rx_status & DSIZE) - CRC_SIZE;
-
- if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
- printf
- ("natsemi_poll: Corrupted packet received, buffer status = %X\n",
- rx_status);
- retstat = 0;
- } else { /* give packet to higher level routine */
- net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE),
- length);
- retstat = 1;
- }
-
- /* return the descriptor and buffer to receive ring */
- rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
- rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
-
- if (++cur_rx == NUM_RX_DESC)
- cur_rx = 0;
-
- /* re-enable the potentially idle receive state machine */
- OUTL(dev, RxOn, ChipCmd);
-
- return retstat;
-}
-
-/* Function: natsemi_disable
- *
- * Description: Turns off interrupts and stops Tx and Rx engines
- *
- * Arguments: struct eth_device *dev: NIC data structure
- *
- * Returns: void.
- */
-
-static void
-natsemi_disable(struct eth_device *dev)
-{
- /* Disable interrupts using the mask. */
- OUTL(dev, 0, IntrMask);
- OUTL(dev, 0, IntrEnable);
-
- /* Stop the chip's Tx and Rx processes. */
- OUTL(dev, RxOff | TxOff, ChipCmd);
-
- /* Restore PME enable bit */
- OUTL(dev, SavedClkRun, ClkRun);
-}
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 08/10] net: Remove ns8382x driver
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
` (5 preceding siblings ...)
2022-03-31 17:46 ` [PATCH 07/10] net: Remove natsemi driver Tom Rini
@ 2022-03-31 17:46 ` Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 09/10] net: Remove uli526x driver Tom Rini
` (2 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
This driver is not enabled by any board and not converted to DM_ETH.
Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/net/Makefile | 1 -
drivers/net/ns8382x.c | 854 ------------------------------------------
2 files changed, 855 deletions(-)
delete mode 100644 drivers/net/ns8382x.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index f902f0d06c26..02b36582ce46 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -67,7 +67,6 @@ obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NETCONSOLE) += netconsole.o
obj-$(CONFIG_NET_OCTEONTX) += octeontx/
obj-$(CONFIG_NET_OCTEONTX2) += octeontx2/
-obj-$(CONFIG_NS8382X) += ns8382x.o
obj-$(CONFIG_OCTEONTX2_CGX_INTF) += octeontx2/cgx_intf.o
obj-$(CONFIG_OCTEONTX_SMI) += octeontx/smi.o
obj-$(CONFIG_PCH_GBE) += pch_gbe.o
diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c
deleted file mode 100644
index d79872af0936..000000000000
--- a/drivers/net/ns8382x.c
+++ /dev/null
@@ -1,854 +0,0 @@
-/*
- ns8382x.c: A U-Boot driver for the NatSemi DP8382[01].
- ported by: Mark A. Rakes (mark_rakes@vivato.net)
-
- Adapted from:
- 1. an Etherboot driver for DP8381[56] written by:
- Copyright (C) 2001 Entity Cyber, Inc.
-
- This development of this Etherboot driver was funded by
- Sicom Systems: http://www.sicompos.com/
-
- Author: Marty Connor (mdc@thinguin.org)
- Adapted from a Linux driver which was written by Donald Becker
-
- This software may be used and distributed according to the terms
- of the GNU Public License (GPL), incorporated herein by reference.
-
- 2. A Linux driver by Donald Becker, ns820.c:
- Written/copyright 1999-2002 by Donald Becker.
-
- This software may be used and distributed according to the terms of
- the GNU General Public License (GPL), incorporated herein by reference.
- Drivers based on or derived from this code fall under the GPL and must
- retain the authorship, copyright and license notice. This file is not
- a complete program and may only be used when the entire operating
- system is licensed under the GPL. License for under other terms may be
- available. Contact the original author for details.
-
- The original author may be reached as becker@scyld.com, or at
- Scyld Computing Corporation
- 410 Severn Ave., Suite 210
- Annapolis MD 21403
-
- Support information and updates available at
- http://www.scyld.com/network/netsemi.html
-
- Datasheets available from:
- http://www.national.com/pf/DP/DP83820.html
- http://www.national.com/pf/DP/DP83821.html
-*/
-
-/* Revision History
- * October 2002 mar 1.0
- * Initial U-Boot Release.
- * Tested with Netgear GA622T (83820)
- * and SMC9452TX (83821)
- * NOTE: custom boards with these chips may (likely) require
- * a programmed EEPROM device (if present) in order to work
- * correctly.
-*/
-
-/* Includes */
-#include <common.h>
-#include <log.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <linux/delay.h>
-
-/* defines */
-#define DSIZE 0x00000FFF
-#define CRC_SIZE 4
-#define TOUT_LOOP 500000
-#define TX_BUF_SIZE 1536
-#define RX_BUF_SIZE 1536
-#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
-
-enum register_offsets {
- ChipCmd = 0x00,
- ChipConfig = 0x04,
- EECtrl = 0x08,
- IntrMask = 0x14,
- IntrEnable = 0x18,
- TxRingPtr = 0x20,
- TxRingPtrHi = 0x24,
- TxConfig = 0x28,
- RxRingPtr = 0x30,
- RxRingPtrHi = 0x34,
- RxConfig = 0x38,
- PriQueue = 0x3C,
- RxFilterAddr = 0x48,
- RxFilterData = 0x4C,
- ClkRun = 0xCC,
- PCIPM = 0x44,
-};
-
-enum ChipCmdBits {
- ChipReset = 0x100,
- RxReset = 0x20,
- TxReset = 0x10,
- RxOff = 0x08,
- RxOn = 0x04,
- TxOff = 0x02,
- TxOn = 0x01
-};
-
-enum ChipConfigBits {
- LinkSts = 0x80000000,
- GigSpeed = 0x40000000,
- HundSpeed = 0x20000000,
- FullDuplex = 0x10000000,
- TBIEn = 0x01000000,
- Mode1000 = 0x00400000,
- T64En = 0x00004000,
- D64En = 0x00001000,
- M64En = 0x00000800,
- PhyRst = 0x00000400,
- PhyDis = 0x00000200,
- ExtStEn = 0x00000100,
- BEMode = 0x00000001,
-};
-#define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex)
-
-enum TxConfig_bits {
- TxDrthMask = 0x000000ff,
- TxFlthMask = 0x0000ff00,
- TxMxdmaMask = 0x00700000,
- TxMxdma_8 = 0x00100000,
- TxMxdma_16 = 0x00200000,
- TxMxdma_32 = 0x00300000,
- TxMxdma_64 = 0x00400000,
- TxMxdma_128 = 0x00500000,
- TxMxdma_256 = 0x00600000,
- TxMxdma_512 = 0x00700000,
- TxMxdma_1024 = 0x00000000,
- TxCollRetry = 0x00800000,
- TxAutoPad = 0x10000000,
- TxMacLoop = 0x20000000,
- TxHeartIgn = 0x40000000,
- TxCarrierIgn = 0x80000000
-};
-
-enum RxConfig_bits {
- RxDrthMask = 0x0000003e,
- RxMxdmaMask = 0x00700000,
- RxMxdma_8 = 0x00100000,
- RxMxdma_16 = 0x00200000,
- RxMxdma_32 = 0x00300000,
- RxMxdma_64 = 0x00400000,
- RxMxdma_128 = 0x00500000,
- RxMxdma_256 = 0x00600000,
- RxMxdma_512 = 0x00700000,
- RxMxdma_1024 = 0x00000000,
- RxAcceptLenErr = 0x04000000,
- RxAcceptLong = 0x08000000,
- RxAcceptTx = 0x10000000,
- RxStripCRC = 0x20000000,
- RxAcceptRunt = 0x40000000,
- RxAcceptErr = 0x80000000,
-};
-
-/* Bits in the RxMode register. */
-enum rx_mode_bits {
- RxFilterEnable = 0x80000000,
- AcceptAllBroadcast = 0x40000000,
- AcceptAllMulticast = 0x20000000,
- AcceptAllUnicast = 0x10000000,
- AcceptPerfectMatch = 0x08000000,
-};
-
-typedef struct _BufferDesc {
- u32 link;
- u32 bufptr;
- vu_long cmdsts;
- u32 extsts; /*not used here */
-} BufferDesc;
-
-/* Bits in network_desc.status */
-enum desc_status_bits {
- DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
- DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
- DescSizeMask = 0xfff,
-
- DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
- DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
- DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
- DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
-
- DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
- DescRxDest = 0x01800000, DescRxLong = 0x00400000,
- DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
- DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
- DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
-};
-
-/* Bits in MEAR */
-enum mii_reg_bits {
- MDIO_ShiftClk = 0x0040,
- MDIO_EnbOutput = 0x0020,
- MDIO_Data = 0x0010,
-};
-
-/* PHY Register offsets. */
-enum phy_reg_offsets {
- BMCR = 0x00,
- BMSR = 0x01,
- PHYIDR1 = 0x02,
- PHYIDR2 = 0x03,
- ANAR = 0x04,
- KTCR = 0x09,
-};
-
-/* basic mode control register bits */
-enum bmcr_bits {
- Bmcr_Reset = 0x8000,
- Bmcr_Loop = 0x4000,
- Bmcr_Speed0 = 0x2000,
- Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */
- Bmcr_RstAutoNeg = 0x0200,
- Bmcr_Duplex = 0x0100,
- Bmcr_Speed1 = 0x0040,
- Bmcr_Force10H = 0x0000,
- Bmcr_Force10F = 0x0100,
- Bmcr_Force100H = 0x2000,
- Bmcr_Force100F = 0x2100,
- Bmcr_Force1000H = 0x0040,
- Bmcr_Force1000F = 0x0140,
-};
-
-/* auto negotiation advertisement register */
-enum anar_bits {
- anar_adv_100F = 0x0100,
- anar_adv_100H = 0x0080,
- anar_adv_10F = 0x0040,
- anar_adv_10H = 0x0020,
- anar_ieee_8023 = 0x0001,
-};
-
-/* 1K-base T control register */
-enum ktcr_bits {
- ktcr_adv_1000H = 0x0100,
- ktcr_adv_1000F = 0x0200,
-};
-
-/* Globals */
-static u32 SavedClkRun;
-static unsigned int cur_rx;
-static unsigned int rx_config;
-static unsigned int tx_config;
-
-/* Note: transmit and receive buffers and descriptors must be
- long long word aligned */
-static BufferDesc txd __attribute__ ((aligned(8)));
-static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8)));
-static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8)));
-static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
- __attribute__ ((aligned(8)));
-
-/* Function Prototypes */
-static int mdio_read(struct eth_device *dev, int phy_id, int addr);
-static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value);
-static void mdio_sync(struct eth_device *dev, u32 offset);
-static int ns8382x_init(struct eth_device *dev, struct bd_info * bis);
-static void ns8382x_reset(struct eth_device *dev);
-static void ns8382x_init_rxfilter(struct eth_device *dev);
-static void ns8382x_init_txd(struct eth_device *dev);
-static void ns8382x_init_rxd(struct eth_device *dev);
-static void ns8382x_set_rx_mode(struct eth_device *dev);
-static void ns8382x_check_duplex(struct eth_device *dev);
-static int ns8382x_send(struct eth_device *dev, void *packet, int length);
-static int ns8382x_poll(struct eth_device *dev);
-static void ns8382x_disable(struct eth_device *dev);
-
-static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820},
- {}
-};
-
-#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
-
-static inline int
-INW(struct eth_device *dev, u_long addr)
-{
- return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
-}
-
-static int
-INL(struct eth_device *dev, u_long addr)
-{
- return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
-}
-
-static inline void
-OUTW(struct eth_device *dev, int command, u_long addr)
-{
- *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
-}
-
-static inline void
-OUTL(struct eth_device *dev, int command, u_long addr)
-{
- *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
-}
-
-/* Function: ns8382x_initialize
- * Description: Retrieves the MAC address of the card, and sets up some
- * globals required by other routines, and initializes the NIC, making it
- * ready to send and receive packets.
- * Side effects: initializes ns8382xs, ready to receive packets.
- * Returns: int: number of cards found
- */
-
-int
-ns8382x_initialize(struct bd_info * bis)
-{
- pci_dev_t devno;
- int card_number = 0;
- struct eth_device *dev;
- u32 iobase, status;
- int i, idx = 0;
- u32 phyAddress;
- u32 tmp;
- u32 chip_config;
-
- while (1) { /* Find PCI device(s) */
- if ((devno = pci_find_devices(supported, idx++)) < 0)
- break;
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
- iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
-
- debug("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase);
-
- pci_write_config_dword(devno, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Check if I/O accesses and Bus Mastering are enabled. */
- pci_read_config_dword(devno, PCI_COMMAND, &status);
- if (!(status & PCI_COMMAND_MEMORY)) {
- printf("Error: Can not enable MEM access.\n");
- continue;
- } else if (!(status & PCI_COMMAND_MASTER)) {
- printf("Error: Can not enable Bus Mastering.\n");
- continue;
- }
-
- dev = (struct eth_device *) malloc(sizeof *dev);
- if (!dev) {
- printf("ns8382x: Can not allocate memory\n");
- break;
- }
- memset(dev, 0, sizeof(*dev));
-
- sprintf(dev->name, "dp8382x#%d", card_number);
- dev->iobase = bus_to_phys(iobase);
- dev->priv = (void *) devno;
- dev->init = ns8382x_init;
- dev->halt = ns8382x_disable;
- dev->send = ns8382x_send;
- dev->recv = ns8382x_poll;
-
- /* ns8382x has a non-standard PM control register
- * in PCI config space. Some boards apparently need
- * to be brought to D0 in this manner. */
- pci_read_config_dword(devno, PCIPM, &tmp);
- if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */
- u32 newtmp = tmp & ~(0x03 | 0x100);
- pci_write_config_dword(devno, PCIPM, newtmp);
- }
-
- /* get MAC address */
- for (i = 0; i < 3; i++) {
- u32 data;
- char *mac = (char *)&dev->enetaddr[i * 2];
-
- OUTL(dev, i * 2, RxFilterAddr);
- data = INL(dev, RxFilterData);
- *mac++ = data;
- *mac++ = data >> 8;
- }
- /* get PHY address, can't be zero */
- for (phyAddress = 1; phyAddress < 32; phyAddress++) {
- u32 rev, phy1;
-
- phy1 = mdio_read(dev, phyAddress, PHYIDR1);
- if (phy1 == 0x2000) { /*check for 83861/91 */
- rev = mdio_read(dev, phyAddress, PHYIDR2);
- if ((rev & ~(0x000f)) == 0x00005c50 ||
- (rev & ~(0x000f)) == 0x00005c60) {
- debug("phy rev is %x\n", rev);
- debug("phy address is %x\n",
- phyAddress);
- break;
- }
- }
- }
-
- /* set phy to autonegotiate && advertise everything */
- mdio_write(dev, phyAddress, KTCR,
- (ktcr_adv_1000H | ktcr_adv_1000F));
- mdio_write(dev, phyAddress, ANAR,
- (anar_adv_100F | anar_adv_100H | anar_adv_10H |
- anar_adv_10F | anar_ieee_8023));
- mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */
- mdio_write(dev, phyAddress, BMCR,
- (Bmcr_AutoNegEn | Bmcr_RstAutoNeg));
- /* Reset the chip to erase any previous misconfiguration. */
- OUTL(dev, (ChipReset), ChipCmd);
-
- chip_config = INL(dev, ChipConfig);
- /* reset the phy */
- OUTL(dev, (chip_config | PhyRst), ChipConfig);
- /* power up and initialize transceiver */
- OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig);
-
- mdio_sync(dev, EECtrl);
-
- {
- u32 chpcfg =
- INL(dev, ChipConfig) ^ SpeedStatus_Polarity;
-
- debug("%s: Transceiver 10%s %s duplex.\n", dev->name,
- (chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed)
- ? "0" : "",
- chpcfg & FullDuplex ? "full" : "half");
- debug("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
- dev->enetaddr[0], dev->enetaddr[1],
- dev->enetaddr[2], dev->enetaddr[3],
- dev->enetaddr[4], dev->enetaddr[5]);
- }
-
- /* Disable PME:
- * The PME bit is initialized from the EEPROM contents.
- * PCI cards probably have PME disabled, but motherboard
- * implementations may have PME set to enable WakeOnLan.
- * With PME set the chip will scan incoming packets but
- * nothing will be written to memory. */
- SavedClkRun = INL(dev, ClkRun);
- OUTL(dev, SavedClkRun & ~0x100, ClkRun);
-
- eth_register(dev);
-
- card_number++;
-
- pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60);
-
- udelay(10 * 1000);
- }
- return card_number;
-}
-
-/* MII transceiver control section.
- Read and write MII registers using software-generated serial MDIO
- protocol. See the MII specifications or DP83840A data sheet for details.
-
- The maximum data clock rate is 2.5 MHz. To meet minimum timing we
- must flush writes to the PCI bus with a PCI read. */
-#define mdio_delay(mdio_addr) INL(dev, mdio_addr)
-
-#define MDIO_EnbIn (0)
-#define MDIO_WRITE0 (MDIO_EnbOutput)
-#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
-
-/* Generate the preamble required for initial synchronization and
- a few older transceivers. */
-static void
-mdio_sync(struct eth_device *dev, u32 offset)
-{
- int bits = 32;
-
- /* Establish sync by sending at least 32 logic ones. */
- while (--bits >= 0) {
- OUTL(dev, MDIO_WRITE1, offset);
- mdio_delay(offset);
- OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset);
- mdio_delay(offset);
- }
-}
-
-static int
-mdio_read(struct eth_device *dev, int phy_id, int addr)
-{
- int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr;
- int i, retval = 0;
-
- /* Shift the read command bits out. */
- for (i = 15; i >= 0; i--) {
- int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
-
- OUTL(dev, dataval, EECtrl);
- mdio_delay(EECtrl);
- OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
- mdio_delay(EECtrl);
- }
- /* Read the two transition, 16 data, and wire-idle bits. */
- for (i = 19; i > 0; i--) {
- OUTL(dev, MDIO_EnbIn, EECtrl);
- mdio_delay(EECtrl);
- retval =
- (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0);
- OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
- mdio_delay(EECtrl);
- }
- return (retval >> 1) & 0xffff;
-}
-
-static void
-mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
-{
- int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value;
- int i;
-
- /* Shift the command bits out. */
- for (i = 31; i >= 0; i--) {
- int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
-
- OUTL(dev, dataval, EECtrl);
- mdio_delay(EECtrl);
- OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
- mdio_delay(EECtrl);
- }
- /* Clear out extra bits. */
- for (i = 2; i > 0; i--) {
- OUTL(dev, MDIO_EnbIn, EECtrl);
- mdio_delay(EECtrl);
- OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
- mdio_delay(EECtrl);
- }
- return;
-}
-
-/* Function: ns8382x_init
- * Description: resets the ethernet controller chip and configures
- * registers and data structures required for sending and receiving packets.
- * Arguments: struct eth_device *dev: NIC data structure
- * returns: int.
- */
-
-static int
-ns8382x_init(struct eth_device *dev, struct bd_info * bis)
-{
- u32 config;
-
- ns8382x_reset(dev);
-
- /* Disable PME:
- * The PME bit is initialized from the EEPROM contents.
- * PCI cards probably have PME disabled, but motherboard
- * implementations may have PME set to enable WakeOnLan.
- * With PME set the chip will scan incoming packets but
- * nothing will be written to memory. */
- OUTL(dev, SavedClkRun & ~0x100, ClkRun);
-
- ns8382x_init_rxfilter(dev);
- ns8382x_init_txd(dev);
- ns8382x_init_rxd(dev);
-
- /*set up ChipConfig */
- config = INL(dev, ChipConfig);
- /*turn off 64 bit ops && Ten-bit interface
- * && big-endian mode && extended status */
- config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn);
- OUTL(dev, config, ChipConfig);
-
- /* Configure the PCI bus bursts and FIFO thresholds. */
- tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad
- | TxCollRetry | TxMxdma_1024 | (0x1002);
- rx_config = RxMxdma_1024 | 0x20;
-
- debug("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
- debug("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
-
- OUTL(dev, tx_config, TxConfig);
- OUTL(dev, rx_config, RxConfig);
-
- /*turn off priority queueing */
- OUTL(dev, 0x0, PriQueue);
-
- ns8382x_check_duplex(dev);
- ns8382x_set_rx_mode(dev);
-
- OUTL(dev, (RxOn | TxOn), ChipCmd);
- return 1;
-}
-
-/* Function: ns8382x_reset
- * Description: soft resets the controller chip
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: void.
- */
-static void
-ns8382x_reset(struct eth_device *dev)
-{
- OUTL(dev, ChipReset, ChipCmd);
- while (INL(dev, ChipCmd))
- /*wait until done */ ;
- OUTL(dev, 0, IntrMask);
- OUTL(dev, 0, IntrEnable);
-}
-
-/* Function: ns8382x_init_rxfilter
- * Description: sets receive filter address to our MAC address
- * Arguments: struct eth_device *dev: NIC data structure
- * returns: void.
- */
-
-static void
-ns8382x_init_rxfilter(struct eth_device *dev)
-{
- int i;
-
- for (i = 0; i < ETH_ALEN; i += 2) {
- OUTL(dev, i, RxFilterAddr);
- OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
- RxFilterData);
- }
-}
-
-/* Function: ns8382x_init_txd
- * Description: initializes the Tx descriptor
- * Arguments: struct eth_device *dev: NIC data structure
- * returns: void.
- */
-
-static void
-ns8382x_init_txd(struct eth_device *dev)
-{
- txd.link = (u32) 0;
- txd.bufptr = cpu_to_le32((u32) & txb[0]);
- txd.cmdsts = (u32) 0;
- txd.extsts = (u32) 0;
-
- OUTL(dev, 0x0, TxRingPtrHi);
- OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
-
- debug("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n",
- INL(dev, TxRingPtr), &txd);
-}
-
-/* Function: ns8382x_init_rxd
- * Description: initializes the Rx descriptor ring
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: void.
- */
-
-static void
-ns8382x_init_rxd(struct eth_device *dev)
-{
- int i;
-
- OUTL(dev, 0x0, RxRingPtrHi);
-
- cur_rx = 0;
- for (i = 0; i < NUM_RX_DESC; i++) {
- rxd[i].link =
- cpu_to_le32((i + 1 <
- NUM_RX_DESC) ? (u32) & rxd[i +
- 1] : (u32) &
- rxd[0]);
- rxd[i].extsts = cpu_to_le32((u32) 0x0);
- rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
- rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
-
- debug
- ("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
- i, &rxd[i], le32_to_cpu(rxd[i].link),
- le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
- }
- OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr);
-
- debug("ns8382x_init_rxd: RX descriptor register loaded with: %X\n",
- INL(dev, RxRingPtr));
-}
-
-/* Function: ns8382x_set_rx_mode
- * Description:
- * sets the receive mode to accept all broadcast packets and packets
- * with our MAC address, and reject all multicast packets.
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: void.
- */
-
-static void
-ns8382x_set_rx_mode(struct eth_device *dev)
-{
- u32 rx_mode = 0x0;
- /*spec says RxFilterEnable has to be 0 for rest of
- * this stuff to be properly configured. Linux driver
- * seems to support this*/
-/* OUTL(dev, rx_mode, RxFilterAddr);*/
- rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch);
- OUTL(dev, rx_mode, RxFilterAddr);
- printf("ns8382x_set_rx_mode: set to %X\n", rx_mode);
- /*now we turn RxFilterEnable back on */
- /*rx_mode |= RxFilterEnable;
- OUTL(dev, rx_mode, RxFilterAddr);*/
-}
-
-static void
-ns8382x_check_duplex(struct eth_device *dev)
-{
- int gig = 0;
- int hun = 0;
- int duplex = 0;
- int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity);
-
- duplex = (config & FullDuplex) ? 1 : 0;
- gig = (config & GigSpeed) ? 1 : 0;
- hun = (config & HundSpeed) ? 1 : 0;
-
- debug("%s: Setting 10%s %s-duplex based on negotiated link"
- " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
- duplex ? "full" : "half");
-
- if (duplex) {
- rx_config |= RxAcceptTx;
- tx_config |= (TxCarrierIgn | TxHeartIgn);
- } else {
- rx_config &= ~RxAcceptTx;
- tx_config &= ~(TxCarrierIgn | TxHeartIgn);
- }
-
- debug("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
- debug("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
-
- OUTL(dev, tx_config, TxConfig);
- OUTL(dev, rx_config, RxConfig);
-
- /*if speed is 10 or 100, remove MODE1000,
- * if it's 1000, then set it */
- config = INL(dev, ChipConfig);
- if (gig)
- config |= Mode1000;
- else
- config &= ~Mode1000;
-
- debug("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns");
-
- OUTL(dev, config, ChipConfig);
-}
-
-/* Function: ns8382x_send
- * Description: transmits a packet and waits for completion or timeout.
- * Returns: void. */
-static int ns8382x_send(struct eth_device *dev, void *packet, int length)
-{
- u32 i, status = 0;
- vu_long tx_stat = 0;
-
- /* Stop the transmitter */
- OUTL(dev, TxOff, ChipCmd);
-
- debug("ns8382x_send: sending %d bytes\n", (int)length);
-
- /* set the transmit buffer descriptor and enable Transmit State Machine */
- txd.link = cpu_to_le32(0x0);
- txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet));
- txd.extsts = cpu_to_le32(0x0);
- txd.cmdsts = cpu_to_le32(DescOwn | length);
-
- /* load Transmit Descriptor Register */
- OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
-
- debug("ns8382x_send: TX descriptor register loaded with: %#08X\n",
- INL(dev, TxRingPtr));
- debug("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n",
- le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
- le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
-
- /* restart the transmitter */
- OUTL(dev, TxOn, ChipCmd);
-
- for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
- if (i >= TOUT_LOOP) {
- printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n",
- dev->name, tx_stat);
- goto Done;
- }
- }
-
- if (!(tx_stat & DescPktOK)) {
- printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat);
- goto Done;
- }
-
- debug("ns8382x_send: tx_stat: %#08lX\n", tx_stat);
-
- status = 1;
-Done:
- return status;
-}
-
-/* Function: ns8382x_poll
- * Description: checks for a received packet and returns it if found.
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: 1 if packet was received.
- * 0 if no packet was received.
- * Side effects:
- * Returns (copies) the packet to the array dev->packet.
- * Returns the length of the packet.
- */
-
-static int
-ns8382x_poll(struct eth_device *dev)
-{
- int retstat = 0;
- int length = 0;
- vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
-
- if (!(rx_status & (u32) DescOwn))
- return retstat;
-
- debug("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n",
- cur_rx, rx_status);
-
- length = (rx_status & DSIZE) - CRC_SIZE;
-
- if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
- /* corrupted packet received */
- printf("ns8382x_poll: Corrupted packet, status:%lx\n",
- rx_status);
- retstat = 0;
- } else {
- /* give packet to higher level routine */
- net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE),
- length);
- retstat = 1;
- }
-
- /* return the descriptor and buffer to receive ring */
- rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
- rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
-
- if (++cur_rx == NUM_RX_DESC)
- cur_rx = 0;
-
- /* re-enable the potentially idle receive state machine */
- OUTL(dev, RxOn, ChipCmd);
-
- return retstat;
-}
-
-/* Function: ns8382x_disable
- * Description: Turns off interrupts and stops Tx and Rx engines
- * Arguments: struct eth_device *dev: NIC data structure
- * Returns: void.
- */
-
-static void
-ns8382x_disable(struct eth_device *dev)
-{
- /* Disable interrupts using the mask. */
- OUTL(dev, 0, IntrMask);
- OUTL(dev, 0, IntrEnable);
-
- /* Stop the chip's Tx and Rx processes. */
- OUTL(dev, (RxOff | TxOff), ChipCmd);
-
- /* Restore PME enable bit */
- OUTL(dev, SavedClkRun, ClkRun);
-}
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 09/10] net: Remove uli526x driver
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
` (6 preceding siblings ...)
2022-03-31 17:46 ` [PATCH 08/10] net: Remove ns8382x driver Tom Rini
@ 2022-03-31 17:46 ` Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 10/10] arm: Remove unused ep93xx code Tom Rini
2022-04-08 18:04 ` [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
9 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
This driver is not enabled by any board and not converted to DM_ETH.
Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
drivers/net/Makefile | 1 -
drivers/net/uli526x.c | 996 ------------------------------------------
2 files changed, 997 deletions(-)
delete mode 100644 drivers/net/uli526x.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 02b36582ce46..69570bebb447 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -85,7 +85,6 @@ obj-$(CONFIG_SUN4I_EMAC) += sunxi_emac.o
obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_TULIP) += dc2114x.o
-obj-$(CONFIG_ULI526X) += uli526x.o
obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c
deleted file mode 100644
index 3191868cae5a..000000000000
--- a/drivers/net/uli526x.c
+++ /dev/null
@@ -1,996 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007, 2010 Freescale Semiconductor, Inc.
- *
- * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
- *
- * Description:
- * ULI 526x Ethernet port driver.
- * Based on the Linux driver: drivers/net/tulip/uli526x.c
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-
-/* some kernel function compatible define */
-
-#undef DEBUG
-
-/* Board/System/Debug information/definition */
-#define ULI_VENDOR_ID 0x10B9
-#define ULI5261_DEVICE_ID 0x5261
-#define ULI5263_DEVICE_ID 0x5263
-/* ULi M5261 ID*/
-#define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
-/* ULi M5263 ID*/
-#define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
-
-#define ULI526X_IO_SIZE 0x100
-#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
-#define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
-#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
-#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
-#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
-#define TX_BUF_ALLOC 0x300
-#define RX_ALLOC_SIZE PKTSIZE
-#define ULI526X_RESET 1
-#define CR0_DEFAULT 0
-#define CR6_DEFAULT 0x22200000
-#define CR7_DEFAULT 0x180c1
-#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
-#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
-#define MAX_PACKET_SIZE 1514
-#define ULI5261_MAX_MULTICAST 14
-#define RX_COPY_SIZE 100
-#define MAX_CHECK_PACKET 0x8000
-
-#define ULI526X_10MHF 0
-#define ULI526X_100MHF 1
-#define ULI526X_10MFD 4
-#define ULI526X_100MFD 5
-#define ULI526X_AUTO 8
-
-#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
-#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
-#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
-#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
-#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
-#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
-
-/* CR9 definition: SROM/MII */
-#define CR9_SROM_READ 0x4800
-#define CR9_SRCS 0x1
-#define CR9_SRCLK 0x2
-#define CR9_CRDOUT 0x8
-#define SROM_DATA_0 0x0
-#define SROM_DATA_1 0x4
-#define PHY_DATA_1 0x20000
-#define PHY_DATA_0 0x00000
-#define MDCLKH 0x10000
-
-#define PHY_POWER_DOWN 0x800
-
-#define SROM_V41_CODE 0x14
-
-#define SROM_CLK_WRITE(data, ioaddr) do { \
- outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
- udelay(5); \
- outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
- udelay(5); \
- outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
- udelay(5); \
- } while (0)
-
-/* Structure/enum declaration */
-
-struct tx_desc {
- u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
- char *tx_buf_ptr; /* Data for us */
- struct tx_desc *next_tx_desc;
-};
-
-struct rx_desc {
- u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
- char *rx_buf_ptr; /* Data for us */
- struct rx_desc *next_rx_desc;
-};
-
-struct uli526x_board_info {
- u32 chip_id; /* Chip vendor/Device ID */
- pci_dev_t pdev;
-
- long ioaddr; /* I/O base address */
- u32 cr0_data;
- u32 cr5_data;
- u32 cr6_data;
- u32 cr7_data;
- u32 cr15_data;
-
- /* pointer for memory physical address */
- dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
- dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
- dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
- dma_addr_t first_tx_desc_dma;
- dma_addr_t first_rx_desc_dma;
-
- /* descriptor pointer */
- unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
- unsigned char *buf_pool_start; /* Tx buffer pool align dword */
- unsigned char *desc_pool_ptr; /* descriptor pool memory */
- struct tx_desc *first_tx_desc;
- struct tx_desc *tx_insert_ptr;
- struct tx_desc *tx_remove_ptr;
- struct rx_desc *first_rx_desc;
- struct rx_desc *rx_ready_ptr; /* packet come pointer */
- unsigned long tx_packet_cnt; /* transmitted packet count */
-
- u16 PHY_reg4; /* Saved Phyxcer register 4 value */
-
- u8 media_mode; /* user specify media mode */
- u8 op_mode; /* real work dedia mode */
- u8 phy_addr;
-
- /* NIC SROM data */
- unsigned char srom[128];
-};
-
-enum uli526x_offsets {
- DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
- DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
- DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
- DCR15 = 0x78
-};
-
-enum uli526x_CR6_bits {
- CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
- CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
- CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
-};
-
-/* Global variable declaration -- */
-
-static unsigned char uli526x_media_mode = ULI526X_AUTO;
-
-static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
- __attribute__ ((aligned(32)));
-static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
-
-/* For module input parameter */
-static int mode = 8;
-
-/* function declaration -- */
-static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length);
-static u16 read_srom_word(long, int);
-static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
-static void allocate_rx_buffer(struct uli526x_board_info *);
-static void update_cr6(u32, unsigned long);
-static u16 uli_phy_read(unsigned long, u8, u8, u32);
-static u16 phy_readby_cr10(unsigned long, u8, u8);
-static void uli_phy_write(unsigned long, u8, u8, u16, u32);
-static void phy_writeby_cr10(unsigned long, u8, u8, u16);
-static void phy_write_1bit(unsigned long, u32, u32);
-static u16 phy_read_1bit(unsigned long, u32);
-static int uli526x_rx_packet(struct eth_device *);
-static void uli526x_free_tx_pkt(struct eth_device *,
- struct uli526x_board_info *);
-static void uli526x_reuse_buf(struct rx_desc *);
-static void uli526x_init(struct eth_device *);
-static void uli526x_set_phyxcer(struct uli526x_board_info *);
-
-
-static int uli526x_init_one(struct eth_device *, struct bd_info *);
-static void uli526x_disable(struct eth_device *);
-static void set_mac_addr(struct eth_device *);
-
-static struct pci_device_id uli526x_pci_tbl[] = {
- { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
- { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
- {}
-};
-
-/* ULI526X network board routine */
-
-/*
- * Search ULI526X board, register it
- */
-
-int uli526x_initialize(struct bd_info *bis)
-{
- pci_dev_t devno;
- int card_number = 0;
- struct eth_device *dev;
- struct uli526x_board_info *db; /* board information structure */
-
- u32 iobase;
- int idx = 0;
-
- while (1) {
- /* Find PCI device */
- devno = pci_find_devices(uli526x_pci_tbl, idx++);
- if (devno < 0)
- break;
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
- iobase &= ~0xf;
-
- dev = (struct eth_device *)malloc(sizeof *dev);
- if (!dev) {
- printf("uli526x: Can not allocate memory\n");
- break;
- }
- memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "uli526x#%d", card_number);
- db = (struct uli526x_board_info *)
- malloc(sizeof(struct uli526x_board_info));
-
- dev->priv = db;
- db->pdev = devno;
- dev->iobase = iobase;
-
- dev->init = uli526x_init_one;
- dev->halt = uli526x_disable;
- dev->send = uli526x_start_xmit;
- dev->recv = uli526x_rx_packet;
-
- /* init db */
- db->ioaddr = dev->iobase;
- /* get chip id */
-
- pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
-#ifdef DEBUG
- printf("uli526x: uli526x @0x%x\n", iobase);
- printf("uli526x: chip_id%x\n", db->chip_id);
-#endif
- eth_register(dev);
- card_number++;
- pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
- udelay(10 * 1000);
- }
- return card_number;
-}
-
-static int uli526x_init_one(struct eth_device *dev, struct bd_info *bis)
-{
-
- struct uli526x_board_info *db = dev->priv;
- int i;
-
- switch (mode) {
- case ULI526X_10MHF:
- case ULI526X_100MHF:
- case ULI526X_10MFD:
- case ULI526X_100MFD:
- uli526x_media_mode = mode;
- break;
- default:
- uli526x_media_mode = ULI526X_AUTO;
- break;
- }
-
- /* Allocate Tx/Rx descriptor memory */
- db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
- db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
- if (db->desc_pool_ptr == NULL)
- return -1;
-
- db->buf_pool_ptr = (uchar *)&buf_pool[0];
- db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
- if (db->buf_pool_ptr == NULL)
- return -1;
-
- db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
- db->first_tx_desc_dma = db->desc_pool_dma_ptr;
-
- db->buf_pool_start = db->buf_pool_ptr;
- db->buf_pool_dma_start = db->buf_pool_dma_ptr;
-
-#ifdef DEBUG
- printf("%s(): db->ioaddr= 0x%x\n",
- __FUNCTION__, db->ioaddr);
- printf("%s(): media_mode= 0x%x\n",
- __FUNCTION__, uli526x_media_mode);
- printf("%s(): db->desc_pool_ptr= 0x%x\n",
- __FUNCTION__, db->desc_pool_ptr);
- printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
- __FUNCTION__, db->desc_pool_dma_ptr);
- printf("%s(): db->buf_pool_ptr= 0x%x\n",
- __FUNCTION__, db->buf_pool_ptr);
- printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
- __FUNCTION__, db->buf_pool_dma_ptr);
-#endif
-
- /* read 64 word srom data */
- for (i = 0; i < 64; i++)
- ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
- i));
-
- /* Set Node address */
- if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
- ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
- /* SROM absent, so write MAC address to ID Table */
- set_mac_addr(dev);
- else { /*Exist SROM*/
- for (i = 0; i < 6; i++)
- dev->enetaddr[i] = db->srom[20 + i];
- }
-#ifdef DEBUG
- for (i = 0; i < 6; i++)
- printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
-#endif
- db->PHY_reg4 = 0x1e0;
-
- /* system variable init */
- db->cr6_data = CR6_DEFAULT ;
- db->cr6_data |= ULI526X_TXTH_256;
- db->cr0_data = CR0_DEFAULT;
- uli526x_init(dev);
- return 0;
-}
-
-static void uli526x_disable(struct eth_device *dev)
-{
-#ifdef DEBUG
- printf("uli526x_disable\n");
-#endif
- struct uli526x_board_info *db = dev->priv;
-
- if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
- /* Reset & stop ULI526X board */
- outl(ULI526X_RESET, db->ioaddr + DCR0);
- udelay(5);
- uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
-
- /* reset the board */
- db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
- update_cr6(db->cr6_data, dev->iobase);
- outl(0, dev->iobase + DCR7); /* Disable Interrupt */
- outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
- }
-}
-
-/* Initialize ULI526X board
- * Reset ULI526X board
- * Initialize TX/Rx descriptor chain structure
- * Send the set-up frame
- * Enable Tx/Rx machine
- */
-
-static void uli526x_init(struct eth_device *dev)
-{
-
- struct uli526x_board_info *db = dev->priv;
- u8 phy_tmp;
- u16 phy_value;
- u16 phy_reg_reset;
-
- /* Reset M526x MAC controller */
- outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
- udelay(100);
- outl(db->cr0_data, db->ioaddr + DCR0);
- udelay(5);
-
- /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
- db->phy_addr = 1;
- db->tx_packet_cnt = 0;
- for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
- /* peer add */
- phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
- if (phy_value != 0xffff && phy_value != 0) {
- db->phy_addr = phy_tmp;
- break;
- }
- }
-
-#ifdef DEBUG
- printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
- printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
-#endif
- if (phy_tmp == 32)
- printf("Can not find the phy address!!!");
-
- /* Parser SROM and media mode */
- db->media_mode = uli526x_media_mode;
-
- if (!(inl(db->ioaddr + DCR12) & 0x8)) {
- /* Phyxcer capability setting */
- phy_reg_reset = uli_phy_read(db->ioaddr,
- db->phy_addr, 0, db->chip_id);
- phy_reg_reset = (phy_reg_reset | 0x8000);
- uli_phy_write(db->ioaddr, db->phy_addr, 0,
- phy_reg_reset, db->chip_id);
- udelay(500);
-
- /* Process Phyxcer Media Mode */
- uli526x_set_phyxcer(db);
- }
- /* Media Mode Process */
- if (!(db->media_mode & ULI526X_AUTO))
- db->op_mode = db->media_mode; /* Force Mode */
-
- /* Initialize Transmit/Receive decriptor and CR3/4 */
- uli526x_descriptor_init(db, db->ioaddr);
-
- /* Init CR6 to program M526X operation */
- update_cr6(db->cr6_data, db->ioaddr);
-
- /* Init CR7, interrupt active bit */
- db->cr7_data = CR7_DEFAULT;
- outl(db->cr7_data, db->ioaddr + DCR7);
-
- /* Init CR15, Tx jabber and Rx watchdog timer */
- outl(db->cr15_data, db->ioaddr + DCR15);
-
- /* Enable ULI526X Tx/Rx function */
- db->cr6_data |= CR6_RXSC | CR6_TXSC;
- update_cr6(db->cr6_data, db->ioaddr);
- while (!(inl(db->ioaddr + DCR12) & 0x8))
- udelay(10);
-}
-
-/*
- * Hardware start transmission.
- * Send a packet to media from the upper layer.
- */
-
-static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length)
-{
- struct uli526x_board_info *db = dev->priv;
- struct tx_desc *txptr;
- unsigned int len = length;
- /* Too large packet check */
- if (len > MAX_PACKET_SIZE) {
- printf(": big packet = %d\n", len);
- return 0;
- }
-
- /* No Tx resource check, it never happen nromally */
- if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
- printf("No Tx resource %ld\n", db->tx_packet_cnt);
- return 0;
- }
-
- /* Disable NIC interrupt */
- outl(0, dev->iobase + DCR7);
-
- /* transmit this packet */
- txptr = db->tx_insert_ptr;
- memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
- txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
-
- /* Point to next transmit free descriptor */
- db->tx_insert_ptr = txptr->next_tx_desc;
-
- /* Transmit Packet Process */
- if ((db->tx_packet_cnt < TX_DESC_CNT)) {
- txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
- db->tx_packet_cnt++; /* Ready to send */
- outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
- }
-
- /* Got ULI526X status */
- db->cr5_data = inl(db->ioaddr + DCR5);
- outl(db->cr5_data, db->ioaddr + DCR5);
-
-#ifdef TX_DEBUG
- printf("%s(): length = 0x%x\n", __FUNCTION__, length);
- printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
-#endif
-
- outl(db->cr7_data, dev->iobase + DCR7);
- uli526x_free_tx_pkt(dev, db);
-
- return length;
-}
-
-/*
- * Free TX resource after TX complete
- */
-
-static void uli526x_free_tx_pkt(struct eth_device *dev,
- struct uli526x_board_info *db)
-{
- struct tx_desc *txptr;
- u32 tdes0;
-
- txptr = db->tx_remove_ptr;
- while (db->tx_packet_cnt) {
- tdes0 = le32_to_cpu(txptr->tdes0);
- /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
- if (tdes0 & 0x80000000)
- break;
-
- /* A packet sent completed */
- db->tx_packet_cnt--;
-
- if (tdes0 != 0x7fffffff) {
-#ifdef TX_DEBUG
- printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
-#endif
- if (tdes0 & TDES0_ERR_MASK) {
- if (tdes0 & 0x0002) { /* UnderRun */
- if (!(db->cr6_data & CR6_SFT)) {
- db->cr6_data = db->cr6_data |
- CR6_SFT;
- update_cr6(db->cr6_data,
- db->ioaddr);
- }
- }
- }
- }
-
- txptr = txptr->next_tx_desc;
- }/* End of while */
-
- /* Update TX remove pointer to next */
- db->tx_remove_ptr = txptr;
-}
-
-
-/*
- * Receive the come packet and pass to upper layer
- */
-
-static int uli526x_rx_packet(struct eth_device *dev)
-{
- struct uli526x_board_info *db = dev->priv;
- struct rx_desc *rxptr;
- int rxlen = 0;
- u32 rdes0;
-
- rxptr = db->rx_ready_ptr;
-
- rdes0 = le32_to_cpu(rxptr->rdes0);
-#ifdef RX_DEBUG
- printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0);
-#endif
- if (!(rdes0 & 0x80000000)) { /* packet owner check */
- if ((rdes0 & 0x300) != 0x300) {
- /* A packet without First/Last flag */
- /* reuse this buf */
- printf("A packet without First/Last flag");
- uli526x_reuse_buf(rxptr);
- } else {
- /* A packet with First/Last flag */
- rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
-#ifdef RX_DEBUG
- printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
-#endif
- /* error summary bit check */
- if (rdes0 & 0x8000) {
- /* This is a error packet */
- printf("Error: rdes0: %x\n", rdes0);
- }
-
- if (!(rdes0 & 0x8000) ||
- ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
-
-#ifdef RX_DEBUG
- printf("%s(): rx_skb_ptr =%x\n",
- __FUNCTION__, rxptr->rx_buf_ptr);
- printf("%s(): rxlen =%x\n",
- __FUNCTION__, rxlen);
-
- printf("%s(): buf addr =%x\n",
- __FUNCTION__, rxptr->rx_buf_ptr);
- printf("%s(): rxlen =%x\n",
- __FUNCTION__, rxlen);
- int i;
- for (i = 0; i < 0x20; i++)
- printf("%s(): data[%x] =%x\n",
- __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
-#endif
-
- net_process_received_packet(
- (uchar *)rxptr->rx_buf_ptr, rxlen);
- uli526x_reuse_buf(rxptr);
-
- } else {
- /* Reuse SKB buffer when the packet is error */
- printf("Reuse buffer, rdes0");
- uli526x_reuse_buf(rxptr);
- }
- }
-
- rxptr = rxptr->next_rx_desc;
- }
-
- db->rx_ready_ptr = rxptr;
- return rxlen;
-}
-
-/*
- * Reuse the RX buffer
- */
-
-static void uli526x_reuse_buf(struct rx_desc *rxptr)
-{
-
- if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
- rxptr->rdes0 = cpu_to_le32(0x80000000);
- else
- printf("Buffer reuse method error");
-}
-/*
- * Initialize transmit/Receive descriptor
- * Using Chain structure, and allocate Tx/Rx buffer
- */
-
-static void uli526x_descriptor_init(struct uli526x_board_info *db,
- unsigned long ioaddr)
-{
- struct tx_desc *tmp_tx;
- struct rx_desc *tmp_rx;
- unsigned char *tmp_buf;
- dma_addr_t tmp_tx_dma, tmp_rx_dma;
- dma_addr_t tmp_buf_dma;
- int i;
- /* tx descriptor start pointer */
- db->tx_insert_ptr = db->first_tx_desc;
- db->tx_remove_ptr = db->first_tx_desc;
-
- outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
-
- /* rx descriptor start pointer */
- db->first_rx_desc = (void *)db->first_tx_desc +
- sizeof(struct tx_desc) * TX_DESC_CNT;
- db->first_rx_desc_dma = db->first_tx_desc_dma +
- sizeof(struct tx_desc) * TX_DESC_CNT;
- db->rx_ready_ptr = db->first_rx_desc;
- outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
-#ifdef DEBUG
- printf("%s(): db->first_tx_desc= 0x%x\n",
- __FUNCTION__, db->first_tx_desc);
- printf("%s(): db->first_rx_desc_dma= 0x%x\n",
- __FUNCTION__, db->first_rx_desc_dma);
-#endif
- /* Init Transmit chain */
- tmp_buf = db->buf_pool_start;
- tmp_buf_dma = db->buf_pool_dma_start;
- tmp_tx_dma = db->first_tx_desc_dma;
- for (tmp_tx = db->first_tx_desc, i = 0;
- i < TX_DESC_CNT; i++, tmp_tx++) {
- tmp_tx->tx_buf_ptr = (char *)tmp_buf;
- tmp_tx->tdes0 = cpu_to_le32(0);
- tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
- tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
- tmp_tx_dma += sizeof(struct tx_desc);
- tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
- tmp_tx->next_tx_desc = tmp_tx + 1;
- tmp_buf = tmp_buf + TX_BUF_ALLOC;
- tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
- }
- (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
- tmp_tx->next_tx_desc = db->first_tx_desc;
-
- /* Init Receive descriptor chain */
- tmp_rx_dma = db->first_rx_desc_dma;
- for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
- i++, tmp_rx++) {
- tmp_rx->rdes0 = cpu_to_le32(0);
- tmp_rx->rdes1 = cpu_to_le32(0x01000600);
- tmp_rx_dma += sizeof(struct rx_desc);
- tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
- tmp_rx->next_rx_desc = tmp_rx + 1;
- }
- (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
- tmp_rx->next_rx_desc = db->first_rx_desc;
-
- /* pre-allocate Rx buffer */
- allocate_rx_buffer(db);
-}
-
-/*
- * Update CR6 value
- * Firstly stop ULI526X, then written value and start
- */
-
-static void update_cr6(u32 cr6_data, unsigned long ioaddr)
-{
-
- outl(cr6_data, ioaddr + DCR6);
- udelay(5);
-}
-
-/*
- * Allocate rx buffer,
- */
-
-static void allocate_rx_buffer(struct uli526x_board_info *db)
-{
- int index;
- struct rx_desc *rxptr;
- rxptr = db->first_rx_desc;
- u32 addr;
-
- for (index = 0; index < RX_DESC_CNT; index++) {
- addr = (u32)net_rx_packets[index];
- addr += (16 - (addr & 15));
- rxptr->rx_buf_ptr = (char *) addr;
- rxptr->rdes2 = cpu_to_le32(addr);
- rxptr->rdes0 = cpu_to_le32(0x80000000);
-#ifdef DEBUG
- printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
- printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
- printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
- printf("%s(): rxptr buf address = 0x%x\n", \
- __FUNCTION__, rxptr->rx_buf_ptr);
- printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
-#endif
- rxptr = rxptr->next_rx_desc;
- }
-}
-
-/*
- * Read one word data from the serial ROM
- */
-
-static u16 read_srom_word(long ioaddr, int offset)
-{
- int i;
- u16 srom_data = 0;
- long cr9_ioaddr = ioaddr + DCR9;
-
- outl(CR9_SROM_READ, cr9_ioaddr);
- outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
-
- /* Send the Read Command 110b */
- SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
- SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
- SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
-
- /* Send the offset */
- for (i = 5; i >= 0; i--) {
- srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
- SROM_CLK_WRITE(srom_data, cr9_ioaddr);
- }
-
- outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
-
- for (i = 16; i > 0; i--) {
- outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
- udelay(5);
- srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
- ? 1 : 0);
- outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
- udelay(5);
- }
-
- outl(CR9_SROM_READ, cr9_ioaddr);
- return srom_data;
-}
-
-/*
- * Set 10/100 phyxcer capability
- * AUTO mode : phyxcer register4 is NIC capability
- * Force mode: phyxcer register4 is the force media
- */
-
-static void uli526x_set_phyxcer(struct uli526x_board_info *db)
-{
- u16 phy_reg;
-
- /* Phyxcer capability setting */
- phy_reg = uli_phy_read(db->ioaddr,
- db->phy_addr, 4, db->chip_id) & ~0x01e0;
-
- if (db->media_mode & ULI526X_AUTO) {
- /* AUTO Mode */
- phy_reg |= db->PHY_reg4;
- } else {
- /* Force Mode */
- switch (db->media_mode) {
- case ULI526X_10MHF: phy_reg |= 0x20; break;
- case ULI526X_10MFD: phy_reg |= 0x40; break;
- case ULI526X_100MHF: phy_reg |= 0x80; break;
- case ULI526X_100MFD: phy_reg |= 0x100; break;
- }
-
- }
-
- /* Write new capability to Phyxcer Reg4 */
- if (!(phy_reg & 0x01e0)) {
- phy_reg |= db->PHY_reg4;
- db->media_mode |= ULI526X_AUTO;
- }
- uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
-
- /* Restart Auto-Negotiation */
- uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
- udelay(50);
-}
-
-/*
- * Write a word to Phy register
- */
-
-static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
- u16 phy_data, u32 chip_id)
-{
- u16 i;
- unsigned long ioaddr;
-
- if (chip_id == PCI_ULI5263_ID) {
- phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
- return;
- }
- /* M5261/M5263 Chip */
- ioaddr = iobase + DCR9;
-
- /* Send 33 synchronization clock to Phy controller */
- for (i = 0; i < 35; i++)
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send start command(01) to Phy */
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send write command(01) to Phy */
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send Phy address */
- for (i = 0x10; i > 0; i = i >> 1)
- phy_write_1bit(ioaddr, phy_addr & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-
- /* Send register address */
- for (i = 0x10; i > 0; i = i >> 1)
- phy_write_1bit(ioaddr, offset & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-
- /* written trasnition */
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
-
- /* Write a word data to PHY controller */
- for (i = 0x8000; i > 0; i >>= 1)
- phy_write_1bit(ioaddr, phy_data & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-}
-
-/*
- * Read a word data from phy register
- */
-
-static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
- u32 chip_id)
-{
- int i;
- u16 phy_data;
- unsigned long ioaddr;
-
- if (chip_id == PCI_ULI5263_ID)
- return phy_readby_cr10(iobase, phy_addr, offset);
- /* M5261/M5263 Chip */
- ioaddr = iobase + DCR9;
-
- /* Send 33 synchronization clock to Phy controller */
- for (i = 0; i < 35; i++)
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send start command(01) to Phy */
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
-
- /* Send read command(10) to Phy */
- phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
- phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
-
- /* Send Phy address */
- for (i = 0x10; i > 0; i = i >> 1)
- phy_write_1bit(ioaddr, phy_addr & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-
- /* Send register address */
- for (i = 0x10; i > 0; i = i >> 1)
- phy_write_1bit(ioaddr, offset & i ?
- PHY_DATA_1 : PHY_DATA_0, chip_id);
-
- /* Skip transition state */
- phy_read_1bit(ioaddr, chip_id);
-
- /* read 16bit data */
- for (phy_data = 0, i = 0; i < 16; i++) {
- phy_data <<= 1;
- phy_data |= phy_read_1bit(ioaddr, chip_id);
- }
-
- return phy_data;
-}
-
-static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
-{
- unsigned long ioaddr, cr10_value;
-
- ioaddr = iobase + DCR10;
- cr10_value = phy_addr;
- cr10_value = (cr10_value<<5) + offset;
- cr10_value = (cr10_value<<16) + 0x08000000;
- outl(cr10_value, ioaddr);
- udelay(1);
- while (1) {
- cr10_value = inl(ioaddr);
- if (cr10_value & 0x10000000)
- break;
- }
- return (cr10_value&0x0ffff);
-}
-
-static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
- u8 offset, u16 phy_data)
-{
- unsigned long ioaddr, cr10_value;
-
- ioaddr = iobase + DCR10;
- cr10_value = phy_addr;
- cr10_value = (cr10_value<<5) + offset;
- cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
- outl(cr10_value, ioaddr);
- udelay(1);
-}
-/*
- * Write one bit data to Phy Controller
- */
-
-static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
-{
- outl(phy_data , ioaddr); /* MII Clock Low */
- udelay(1);
- outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
- udelay(1);
- outl(phy_data , ioaddr); /* MII Clock Low */
- udelay(1);
-}
-
-/*
- * Read one bit phy data from PHY controller
- */
-
-static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
-{
- u16 phy_data;
-
- outl(0x50000 , ioaddr);
- udelay(1);
- phy_data = (inl(ioaddr) >> 19) & 0x1;
- outl(0x40000 , ioaddr);
- udelay(1);
-
- return phy_data;
-}
-
-/*
- * Set MAC address to ID Table
- */
-
-static void set_mac_addr(struct eth_device *dev)
-{
- int i;
- u16 addr;
- struct uli526x_board_info *db = dev->priv;
- outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
- /* Reset dianostic pointer port */
- outl(0x1c0, db->ioaddr + DCR13);
- outl(0, db->ioaddr + DCR14); /* Clear reset port */
- outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
- outl(0, db->ioaddr + DCR14); /* Clear reset port */
- outl(0, db->ioaddr + DCR13); /* Clear CR13 */
- /* Select ID Table access port */
- outl(0x1b0, db->ioaddr + DCR13);
- /* Read MAC address from CR14 */
- for (i = 0; i < 3; i++) {
- addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
- outl(addr, db->ioaddr + DCR14);
- }
- /* write end */
- outl(0, db->ioaddr + DCR13); /* Clear CR13 */
- outl(0, db->ioaddr + DCR0); /* Clear CR0 */
- udelay(10);
- return;
-}
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 10/10] arm: Remove unused ep93xx code
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
` (7 preceding siblings ...)
2022-03-31 17:46 ` [PATCH 09/10] net: Remove uli526x driver Tom Rini
@ 2022-03-31 17:46 ` Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-04-08 18:04 ` [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
9 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2022-03-31 17:46 UTC (permalink / raw)
To: u-boot
There are no platforms for this architecture anymore, remove unused
code.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/arm/cpu/arm920t/Makefile | 1 -
arch/arm/cpu/arm920t/ep93xx/Makefile | 19 -
arch/arm/cpu/arm920t/ep93xx/cpu.c | 37 --
arch/arm/cpu/arm920t/ep93xx/led.c | 85 ---
arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S | 457 --------------
arch/arm/cpu/arm920t/ep93xx/speed.c | 96 ---
arch/arm/cpu/arm920t/ep93xx/timer.c | 117 ----
arch/arm/include/asm/arch-ep93xx/ep93xx.h | 666 --------------------
drivers/net/Makefile | 1 -
drivers/net/ep93xx_eth.c | 654 -------------------
drivers/net/ep93xx_eth.h | 126 ----
drivers/usb/host/Makefile | 1 -
drivers/usb/host/ohci-ep93xx.c | 37 --
13 files changed, 2297 deletions(-)
delete mode 100644 arch/arm/cpu/arm920t/ep93xx/Makefile
delete mode 100644 arch/arm/cpu/arm920t/ep93xx/cpu.c
delete mode 100644 arch/arm/cpu/arm920t/ep93xx/led.c
delete mode 100644 arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
delete mode 100644 arch/arm/cpu/arm920t/ep93xx/speed.c
delete mode 100644 arch/arm/cpu/arm920t/ep93xx/timer.c
delete mode 100644 arch/arm/include/asm/arch-ep93xx/ep93xx.h
delete mode 100644 drivers/net/ep93xx_eth.c
delete mode 100644 drivers/net/ep93xx_eth.h
delete mode 100644 drivers/usb/host/ohci-ep93xx.c
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index c63f578f1a95..b70822c67ab9 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -7,7 +7,6 @@ extra-y = start.o
obj-y += cpu.o
-obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
# some files can only build in ARM mode
diff --git a/arch/arm/cpu/arm920t/ep93xx/Makefile b/arch/arm/cpu/arm920t/ep93xx/Makefile
deleted file mode 100644
index 152b5e7c5a2e..000000000000
--- a/arch/arm/cpu/arm920t/ep93xx/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Cirrus Logic EP93xx CPU-specific Makefile
-#
-# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
-#
-# Copyright (C) 2004, 2005
-# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
-#
-# Copyright (C) 2006
-# Dominic Rath <Dominic.Rath@gmx.de>
-#
-# Based on an original Makefile, which is
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = cpu.o led.o speed.o timer.o
-obj-y += lowlevel_init.o
diff --git a/arch/arm/cpu/arm920t/ep93xx/cpu.c b/arch/arm/cpu/arm920t/ep93xx/cpu.c
deleted file mode 100644
index 3435bdc748a2..000000000000
--- a/arch/arm/cpu/arm920t/ep93xx/cpu.c
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic EP93xx CPU-specific support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-
-/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
-extern void reset_cpu(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- uint32_t value;
-
- /* Unlock DeviceCfg and set SWRST */
- writel(0xAA, &syscon->sysswlock);
- value = readl(&syscon->devicecfg);
- value |= SYSCON_DEVICECFG_SWRST;
- writel(value, &syscon->devicecfg);
-
- /* Unlock DeviceCfg and clear SWRST */
- writel(0xAA, &syscon->sysswlock);
- value = readl(&syscon->devicecfg);
- value &= ~SYSCON_DEVICECFG_SWRST;
- writel(value, &syscon->devicecfg);
-
- /* Dying... */
- while (1)
- ; /* noop */
-}
diff --git a/arch/arm/cpu/arm920t/ep93xx/led.c b/arch/arm/cpu/arm920t/ep93xx/led.c
deleted file mode 100644
index 862663acbab5..000000000000
--- a/arch/arm/cpu/arm920t/ep93xx/led.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- */
-
-#include <asm/io.h>
-#include <asm/arch/ep93xx.h>
-#include <config.h>
-#include <status_led.h>
-
-static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
-static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
- 1 << CONFIG_LED_STATUS_RED};
-
-static inline void switch_LED_on(uint8_t led)
-{
- register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
- writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
- saved_state[led] = CONFIG_LED_STATUS_ON;
-}
-
-static inline void switch_LED_off(uint8_t led)
-{
- register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
- writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
- saved_state[led] = CONFIG_LED_STATUS_OFF;
-}
-
-void red_led_on(void)
-{
- switch_LED_on(CONFIG_LED_STATUS_RED);
-}
-
-void red_led_off(void)
-{
- switch_LED_off(CONFIG_LED_STATUS_RED);
-}
-
-void green_led_on(void)
-{
- switch_LED_on(CONFIG_LED_STATUS_GREEN);
-}
-
-void green_led_off(void)
-{
- switch_LED_off(CONFIG_LED_STATUS_GREEN);
-}
-
-void __led_init(led_id_t mask, int state)
-{
- __led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
- if (CONFIG_LED_STATUS_RED == mask) {
- if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
- red_led_off();
- else
- red_led_on();
- } else if (CONFIG_LED_STATUS_GREEN == mask) {
- if (CONFIG_LED_STATUS_ON ==
- saved_state[CONFIG_LED_STATUS_GREEN])
- green_led_off();
- else
- green_led_on();
- }
-}
-
-void __led_set(led_id_t mask, int state)
-{
- if (CONFIG_LED_STATUS_RED == mask) {
- if (CONFIG_LED_STATUS_ON == state)
- red_led_on();
- else
- red_led_off();
- } else if (CONFIG_LED_STATUS_GREEN == mask) {
- if (CONFIG_LED_STATUS_ON == state)
- green_led_on();
- else
- green_led_off();
- }
-}
diff --git a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
deleted file mode 100644
index 5239b1053c25..000000000000
--- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
+++ /dev/null
@@ -1,457 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Low-level initialization for EP93xx
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- * Copyright (C) 2013
- * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
- * Copyright (C) 2006 Cirrus Logic Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- */
-
-#include <config.h>
-#include <asm/arch-ep93xx/ep93xx.h>
-
-/*
-/* Configure the SDRAM based on the supplied settings.
- *
- * Input: r0 - SDRAM DEVCFG register
- * r2 - configuration for SDRAM chips
- * Output: none
- * Modifies: r3, r4
- */
-ep93xx_sdram_config:
- /* Program the SDRAM device configuration register. */
- ldr r3, =SDRAM_BASE
-#ifdef CONFIG_EDB93XX_SDCS0
- str r0, [r3, #SDRAM_OFF_DEVCFG0]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS1
- str r0, [r3, #SDRAM_OFF_DEVCFG1]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS2
- str r0, [r3, #SDRAM_OFF_DEVCFG2]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS3
- str r0, [r3, #SDRAM_OFF_DEVCFG3]
-#endif
-
- /* Set the Initialize and MRS bits (issue continuous NOP commands
- * (INIT & MRS set))
- */
- ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
- EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
- EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
- str r4, [r3, #SDRAM_OFF_GLCONFIG]
-
- /* Delay for 200us. */
- mov r4, #0x3000
-delay1:
- subs r4, r4, #1
- bne delay1
-
- /* Clear the MRS bit to issue a precharge all. */
- ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
- EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
- str r4, [r3, #SDRAM_OFF_GLCONFIG]
-
- /* Temporarily set the refresh timer to 0x10. Make it really low so
- * that refresh cycles are generated.
- */
- ldr r4, =0x10
- str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
-
- /* Delay for at least 80 SDRAM clock cycles. */
- mov r4, #80
-delay2:
- subs r4, r4, #1
- bne delay2
-
- /* Set the refresh timer to the fastest required for any device
- * that might be used. Set 9.6 ms refresh time.
- */
- ldr r4, =0x01e0
- str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
-
- /* Select mode register update mode. */
- ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
- EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
- str r4, [r3, #SDRAM_OFF_GLCONFIG]
-
- /* Program the mode register on the SDRAM by performing fake read */
- ldr r4, [r2]
-
- /* Select normal operating mode. */
- ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
- str r4, [r3, #SDRAM_OFF_GLCONFIG]
-
- /* Return to the caller. */
- mov pc, lr
-
-/*
- * Test to see if the SDRAM has been configured in a usable mode.
- *
- * Input: r0 - Test address of SDRAM
- * Output: r0 - 0 -- Test OK, -1 -- Failed
- * Modifies: r0-r5
- */
-ep93xx_sdram_test:
- /* Load the test patterns to be written to SDRAM. */
- ldr r1, =0xf00dface
- ldr r2, =0xdeadbeef
- ldr r3, =0x08675309
- ldr r4, =0xdeafc0ed
-
- /* Store the test patterns to SDRAM. */
- stmia r0, {r1-r4}
-
- /* Load the test patterns from SDRAM one at a time and compare them
- * to the actual pattern.
- */
- ldr r5, [r0]
- cmp r5, r1
- ldreq r5, [r0, #0x0004]
- cmpeq r5, r2
- ldreq r5, [r0, #0x0008]
- cmpeq r5, r3
- ldreq r5, [r0, #0x000c]
- cmpeq r5, r4
-
- /* Return -1 if a mismatch was encountered, 0 otherwise. */
- mvnne r0, #0xffffffff
- moveq r0, #0x00000000
-
- /* Return to the caller. */
- mov pc, lr
-
-/*
- * Determine the size of the SDRAM. Use data=address for the scan.
- *
- * Input: r0 - Start SDRAM address
- * Return: r0 - Single block size
- * r1 - Valid block mask
- * r2 - Total block count
- * Modifies: r0-r5
- */
-ep93xx_sdram_size:
- /* Store zero at offset zero. */
- str r0, [r0]
-
- /* Start checking for an alias at 1MB into SDRAM. */
- ldr r1, =0x00100000
-
- /* Store the offset at the current offset. */
-check_block_size:
- str r1, [r0, r1]
-
- /* Read back from zero. */
- ldr r2, [r0]
-
- /* Stop searching of an alias was found. */
- cmp r1, r2
- beq found_block_size
-
- /* Advance to the next power of two boundary. */
- mov r1, r1, lsl #1
-
- /* Loop back if the size has not reached 256MB. */
- cmp r1, #0x10000000
- bne check_block_size
-
- /* A full 256MB of memory was found, so return it now. */
- ldr r0, =0x10000000
- ldr r1, =0x00000000
- ldr r2, =0x00000001
- mov pc, lr
-
- /* An alias was found. See if the first block is 128MB in size. */
-found_block_size:
- cmp r1, #0x08000000
-
- /* The first block is 128MB, so there is no further memory. Return it
- * now.
- */
- ldreq r0, =0x08000000
- ldreq r1, =0x00000000
- ldreq r2, =0x00000001
- moveq pc, lr
-
- /* Save the block size, set the block address bits to zero, and
- * initialize the block count to one.
- */
- mov r3, r1
- ldr r4, =0x00000000
- ldr r5, =0x00000001
-
- /* Look for additional blocks of memory by searching for non-aliases. */
-find_blocks:
- /* Store zero back to address zero. It may be overwritten. */
- str r0, [r0]
-
- /* Advance to the next power of two boundary. */
- mov r1, r1, lsl #1
-
- /* Store the offset at the current offset. */
- str r1, [r0, r1]
-
- /* Read back from zero. */
- ldr r2, [r0]
-
- /* See if a non-alias was found. */
- cmp r1, r2
-
- /* If a non-alias was found, then or in the block address bit and
- * multiply the block count by two (since there are two unique
- * blocks, one with this bit zero and one with it one).
- */
- orrne r4, r4, r1
- movne r5, r5, lsl #1
-
- /* Continue searching if there are more address bits to check. */
- cmp r1, #0x08000000
- bne find_blocks
-
- /* Return the block size, address mask, and count. */
- mov r0, r3
- mov r1, r4
- mov r2, r5
-
- /* Return to the caller. */
- mov pc, lr
-
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r6, lr
-
- /* Make sure caches are off and invalidated. */
- ldr r0, =0x00000000
- mcr p15, 0, r0, c1, c0, 0
- nop
- nop
- nop
- nop
- nop
-
- /* Turn off the green LED and turn on the red LED. If the red LED
- * is left on for too long, the external reset circuit described
- * by application note AN258 will cause the system to reset.
- */
- ldr r1, =EP93XX_LED_DATA
- ldr r0, [r1]
- bic r0, r0, #EP93XX_LED_GREEN_ON
- orr r0, r0, #EP93XX_LED_RED_ON
- str r0, [r1]
-
- /* Undo the silly static memory controller programming performed
- * by the boot rom.
- */
- ldr r0, =SMC_BASE
-
- /* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
- ldr r1, =0x0000fbe0
-
- /* Reset EP93XX_OFF_SMCBCR0 */
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR1]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR2]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR3]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR6]
-
- ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
- orr r2, r2, r1
- str r2, [r0, #EP93XX_OFF_SMCBCR7]
-
- /* Set the PLL1 and processor clock. */
- ldr r0, =SYSCON_BASE
-#ifdef CONFIG_EDB9301
- /* 332MHz, giving a 166MHz processor clock. */
- ldr r1, = 0x02b49907
-#else
-
-#ifdef CONFIG_EDB93XX_INDUSTRIAL
- /* 384MHz, giving a 196MHz processor clock. */
- ldr r1, =0x02a4bb38
-#else
- /* 400MHz, giving a 200MHz processor clock. */
- ldr r1, =0x02a4e39e
-#endif
-#endif
- str r1, [r0, #SYSCON_OFF_CLKSET1]
-
- nop
- nop
- nop
- nop
- nop
-
- /* Need to make sure that SDRAM is configured correctly before
- * coping the code into it.
- */
-
-#ifdef CONFIG_EDB93XX_SDCS0
- mov r11, #SDRAM_DEVCFG0_BASE
-#endif
-#ifdef CONFIG_EDB93XX_SDCS1
- mov r11, #SDRAM_DEVCFG1_BASE
-#endif
-#ifdef CONFIG_EDB93XX_SDCS2
- mov r11, #SDRAM_DEVCFG2_BASE
-#endif
-#ifdef CONFIG_EDB93XX_SDCS3
- ldr r0, =SYSCON_BASE
- ldr r0, [r0, #SYSCON_OFF_SYSCFG]
- ands r0, r0, #SYSCON_SYSCFG_LASDO
- moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
- movne r11, #SDRAM_DEVCFG3_ASD1_BASE
-#endif
- /* See Table 13-5 in EP93xx datasheet for more info about DRAM
- * register mapping */
-
- /* Try a 32-bit wide configuration of SDRAM. */
- ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
- EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
- EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
- EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
-
- /* Set burst count: 4 and CAS: 2
- * Burst mode [A11:A10]; CAS [A16:A14]
- */
- orr r2, r11, #0x00008800
- bl ep93xx_sdram_config
-
- /* Test the SDRAM. */
- mov r0, r11
- bl ep93xx_sdram_test
- cmp r0, #0x00000000
- beq ep93xx_sdram_done
-
- /* Try a 16-bit wide configuration of SDRAM. */
- ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
- EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
- EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
- EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
- EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
-
- /* Set burst count: 8, CAS: 2, sequential burst
- * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
- * Burst mode [A10:A9]; CAS [A15:A13]
- */
- orr r2, r11, #0x00004600
- bl ep93xx_sdram_config
-
- /* Test the SDRAM. */
- mov r0, r11
- bl ep93xx_sdram_test
- cmp r0, #0x00000000
- beq ep93xx_sdram_done
-
- /* Turn off the red LED. */
- ldr r0, =EP93XX_LED_DATA
- ldr r1, [r0]
- bic r1, r1, #EP93XX_LED_RED_ON
- str r1, [r0]
-
- /* There is no SDRAM so flash the green LED. */
-flash_green:
- orr r1, r1, #EP93XX_LED_GREEN_ON
- str r1, [r0]
- ldr r2, =0x00010000
-flash_green_delay_1:
- subs r2, r2, #1
- bne flash_green_delay_1
- bic r1, r1, #EP93XX_LED_GREEN_ON
- str r1, [r0]
- ldr r2, =0x00010000
-flash_green_delay_2:
- subs r2, r2, #1
- bne flash_green_delay_2
- orr r1, r1, #EP93XX_LED_GREEN_ON
- str r1, [r0]
- ldr r2, =0x00010000
-flash_green_delay_3:
- subs r2, r2, #1
- bne flash_green_delay_3
- bic r1, r1, #EP93XX_LED_GREEN_ON
- str r1, [r0]
- ldr r2, =0x00050000
-flash_green_delay_4:
- subs r2, r2, #1
- bne flash_green_delay_4
- b flash_green
-
-
-ep93xx_sdram_done:
- ldr r1, =EP93XX_LED_DATA
- ldr r0, [r1]
- bic r0, r0, #EP93XX_LED_RED_ON
- str r0, [r1]
-
- /* Determine the size of the SDRAM. */
- mov r0, r11
- bl ep93xx_sdram_size
-
- /* Save the SDRAM characteristics. */
- mov r8, r0
- mov r9, r1
- mov r10, r2
-
- /* Compute total memory size into r1 */
- mul r1, r8, r10
-#ifdef CONFIG_EDB93XX_SDCS0
- ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS1
- ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS2
- ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
-#endif
-#ifdef CONFIG_EDB93XX_SDCS3
- ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
-#endif
-
- /* Consider small DRAM size as:
- * < 32Mb for 32bit bus
- * < 64Mb for 16bit bus
- */
- tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
- moveq r1, r1, lsr #1
- cmp r1, #0x02000000
-
-#if defined(CONFIG_EDB9301)
- /* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
- movlt r1, #0x03f0
- movge r1, #0x01e0
-#else
- /* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
- movlt r1, #0x0600
- movge r1, #0x2f0
-#endif
- str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
-
- /* Save the memory configuration information. */
- orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
- stmia r0, {r8-r11}
-
- mov lr, r6
- mov pc, lr
diff --git a/arch/arm/cpu/arm920t/ep93xx/speed.c b/arch/arm/cpu/arm920t/ep93xx/speed.c
deleted file mode 100644
index 8dd3904e82c8..000000000000
--- a/arch/arm/cpu/arm920t/ep93xx/speed.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic EP93xx PLL support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-/*
- * get_board_sys_clk() should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-
-/*
- * return the PLL output frequency
- *
- * PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
- * / (X2IPD + 1) / 2^PS
- */
-static ulong get_PLLCLK(uint32_t *pllreg)
-{
- uint8_t i;
- const uint32_t clkset = readl(pllreg);
- uint64_t rate = get_board_sys_clk();
- rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
- rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
- do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
- for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
- rate >>= 1;
-
- return (ulong)rate;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK(void)
-{
- const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
- const uint32_t clkset1 = readl(&syscon->clkset1);
- const uint8_t fclk_div =
- fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
- const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
-
- return fclk_rate;
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
- const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
- const uint32_t clkset1 = readl(&syscon->clkset1);
- const uint8_t hclk_div =
- hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
- const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
-
- return hclk_rate;
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
- const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
- const uint32_t clkset1 = readl(&syscon->clkset1);
- const uint8_t pclk_div =
- pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
- const ulong pclk_rate = get_HCLK() / pclk_div;
-
- return pclk_rate;
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- ulong uclk_rate;
-
- const uint32_t value = readl(&syscon->pwrcnt);
- if (value & SYSCON_PWRCNT_UART_BAUD)
- uclk_rate = get_board_sys_clk();
- else
- uclk_rate = get_board_sys_clk() / 2;
-
- return uclk_rate;
-}
diff --git a/arch/arm/cpu/arm920t/ep93xx/timer.c b/arch/arm/cpu/arm920t/ep93xx/timer.c
deleted file mode 100644
index 892bb06db10e..000000000000
--- a/arch/arm/cpu/arm920t/ep93xx/timer.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic EP93xx timer support.
- *
- * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
- * author unknown.
- */
-
-#include <common.h>
-#include <init.h>
-#include <time.h>
-#include <linux/delay.h>
-#include <linux/types.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-#define TIMER_CLKSEL (1 << 3)
-#define TIMER_ENABLE (1 << 7)
-
-#define TIMER_FREQ 508469 /* ticks / second */
-#define TIMER_MAX_VAL 0xFFFFFFFF
-
-static struct ep93xx_timer
-{
- unsigned long long ticks;
- unsigned long last_read;
-} timer;
-
-static inline unsigned long long usecs_to_ticks(unsigned long usecs)
-{
- unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
- do_div(ticks, 1000 * 1000);
-
- return ticks;
-}
-
-static inline void read_timer(void)
-{
- struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
- const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
-
- if (now >= timer.last_read)
- timer.ticks += now - timer.last_read;
- else
- /* an overflow occurred */
- timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
-
- timer.last_read = now;
-}
-
-/*
- * Get the number of ticks (in CONFIG_SYS_HZ resolution)
- */
-unsigned long long get_ticks(void)
-{
- unsigned long long sys_ticks;
-
- read_timer();
-
- sys_ticks = timer.ticks * CONFIG_SYS_HZ;
- do_div(sys_ticks, TIMER_FREQ);
-
- return sys_ticks;
-}
-
-unsigned long get_timer(unsigned long base)
-{
- return get_ticks() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long target;
-
- read_timer();
-
- target = timer.ticks + usecs_to_ticks(usec);
-
- while (timer.ticks < target)
- read_timer();
-}
-
-int timer_init(void)
-{
- struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
-
- /* use timer 3 with 508KHz and free running, not enabled now */
- writel(TIMER_CLKSEL, &timer_regs->timer3.control);
-
- /* set initial timer value */
- writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
-
- /* Enable the timer */
- writel(TIMER_ENABLE | TIMER_CLKSEL,
- &timer_regs->timer3.control);
-
- /* Reset the timer */
- read_timer();
- timer.ticks = 0;
-
- return 0;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-unsigned long get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h
deleted file mode 100644
index 272b64480d1f..000000000000
--- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h
+++ /dev/null
@@ -1,666 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Cirrus Logic EP93xx register definitions.
- *
- * Copyright (C) 2013
- * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (C) 2009
- * Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006
- * Dominic Rath <Dominic.Rath@gmx.de>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
- *
- * Copyright (C) 2004 Ray Lehtiniemi
- * Copyright (C) 2003 Cirrus Logic, Inc
- * Copyright (C) 1999 ARM Limited.
- */
-
-#define EP93XX_AHB_BASE 0x80000000
-#define EP93XX_APB_BASE 0x80800000
-
-/*
- * 0x80000000 - 0x8000FFFF: DMA
- */
-#define DMA_OFFSET 0x000000
-#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct dma_channel {
- uint32_t control;
- uint32_t interrupt;
- uint32_t ppalloc;
- uint32_t status;
- uint32_t reserved0;
- uint32_t remain;
- uint32_t reserved1[2];
- uint32_t maxcnt0;
- uint32_t base0;
- uint32_t current0;
- uint32_t reserved2;
- uint32_t maxcnt1;
- uint32_t base1;
- uint32_t current1;
- uint32_t reserved3;
-};
-
-struct dma_regs {
- struct dma_channel m2p_channel_0;
- struct dma_channel m2p_channel_1;
- struct dma_channel m2p_channel_2;
- struct dma_channel m2p_channel_3;
- struct dma_channel m2m_channel_0;
- struct dma_channel m2m_channel_1;
- struct dma_channel reserved0[2];
- struct dma_channel m2p_channel_5;
- struct dma_channel m2p_channel_4;
- struct dma_channel m2p_channel_7;
- struct dma_channel m2p_channel_6;
- struct dma_channel m2p_channel_9;
- struct dma_channel m2p_channel_8;
- uint32_t channel_arbitration;
- uint32_t reserved[15];
- uint32_t global_interrupt;
-};
-#endif
-
-/*
- * 0x80010000 - 0x8001FFFF: Ethernet MAC
- */
-#define MAC_OFFSET 0x010000
-#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct mac_queue {
- uint32_t badd;
- union { /* deal with half-word aligned registers */
- uint32_t blen;
- union {
- uint16_t filler;
- uint16_t curlen;
- };
- };
- uint32_t curadd;
-};
-
-struct mac_regs {
- uint32_t rxctl;
- uint32_t txctl;
- uint32_t testctl;
- uint32_t reserved0;
- uint32_t miicmd;
- uint32_t miidata;
- uint32_t miists;
- uint32_t reserved1;
- uint32_t selfctl;
- uint32_t inten;
- uint32_t intstsp;
- uint32_t intstsc;
- uint32_t reserved2[2];
- uint32_t diagad;
- uint32_t diagdata;
- uint32_t gt;
- uint32_t fct;
- uint32_t fcf;
- uint32_t afp;
- union {
- struct {
- uint32_t indad;
- uint32_t indad_upper;
- };
- uint32_t hashtbl;
- };
- uint32_t reserved3[2];
- uint32_t giintsts;
- uint32_t giintmsk;
- uint32_t giintrosts;
- uint32_t giintfrc;
- uint32_t txcollcnt;
- uint32_t rxmissnct;
- uint32_t rxruntcnt;
- uint32_t reserved4;
- uint32_t bmctl;
- uint32_t bmsts;
- uint32_t rxbca;
- uint32_t reserved5;
- struct mac_queue rxdq;
- uint32_t rxdqenq;
- struct mac_queue rxstsq;
- uint32_t rxstsqenq;
- struct mac_queue txdq;
- uint32_t txdqenq;
- struct mac_queue txstsq;
- uint32_t reserved6;
- uint32_t rxbufthrshld;
- uint32_t txbufthrshld;
- uint32_t rxststhrshld;
- uint32_t txststhrshld;
- uint32_t rxdthrshld;
- uint32_t txdthrshld;
- uint32_t maxfrmlen;
- uint32_t maxhdrlen;
-};
-#endif
-
-#define SELFCTL_RWP (1 << 7)
-#define SELFCTL_GPO0 (1 << 5)
-#define SELFCTL_PUWE (1 << 4)
-#define SELFCTL_PDWE (1 << 3)
-#define SELFCTL_MIIL (1 << 2)
-#define SELFCTL_RESET (1 << 0)
-
-#define INTSTS_RWI (1 << 30)
-#define INTSTS_RXMI (1 << 29)
-#define INTSTS_RXBI (1 << 28)
-#define INTSTS_RXSQI (1 << 27)
-#define INTSTS_TXLEI (1 << 26)
-#define INTSTS_ECIE (1 << 25)
-#define INTSTS_TXUHI (1 << 24)
-#define INTSTS_MOI (1 << 18)
-#define INTSTS_TXCOI (1 << 17)
-#define INTSTS_RXROI (1 << 16)
-#define INTSTS_MIII (1 << 12)
-#define INTSTS_PHYI (1 << 11)
-#define INTSTS_TI (1 << 10)
-#define INTSTS_AHBE (1 << 8)
-#define INTSTS_OTHER (1 << 4)
-#define INTSTS_TXSQ (1 << 3)
-#define INTSTS_RXSQ (1 << 2)
-
-#define BMCTL_MT (1 << 13)
-#define BMCTL_TT (1 << 12)
-#define BMCTL_UNH (1 << 11)
-#define BMCTL_TXCHR (1 << 10)
-#define BMCTL_TXDIS (1 << 9)
-#define BMCTL_TXEN (1 << 8)
-#define BMCTL_EH2 (1 << 6)
-#define BMCTL_EH1 (1 << 5)
-#define BMCTL_EEOB (1 << 4)
-#define BMCTL_RXCHR (1 << 2)
-#define BMCTL_RXDIS (1 << 1)
-#define BMCTL_RXEN (1 << 0)
-
-#define BMSTS_TXACT (1 << 7)
-#define BMSTS_TP (1 << 4)
-#define BMSTS_RXACT (1 << 3)
-#define BMSTS_QID_MASK 0x07
-#define BMSTS_QID_RXDATA 0x00
-#define BMSTS_QID_TXDATA 0x01
-#define BMSTS_QID_RXSTS 0x02
-#define BMSTS_QID_TXSTS 0x03
-#define BMSTS_QID_RXDESC 0x04
-#define BMSTS_QID_TXDESC 0x05
-
-#define AFP_MASK 0x07
-#define AFP_IAPRIMARY 0x00
-#define AFP_IASECONDARY1 0x01
-#define AFP_IASECONDARY2 0x02
-#define AFP_IASECONDARY3 0x03
-#define AFP_TX 0x06
-#define AFP_HASH 0x07
-
-#define RXCTL_PAUSEA (1 << 20)
-#define RXCTL_RXFCE1 (1 << 19)
-#define RXCTL_RXFCE0 (1 << 18)
-#define RXCTL_BCRC (1 << 17)
-#define RXCTL_SRXON (1 << 16)
-#define RXCTL_RCRCA (1 << 13)
-#define RXCTL_RA (1 << 12)
-#define RXCTL_PA (1 << 11)
-#define RXCTL_BA (1 << 10)
-#define RXCTL_MA (1 << 9)
-#define RXCTL_IAHA (1 << 8)
-#define RXCTL_IA3 (1 << 3)
-#define RXCTL_IA2 (1 << 2)
-#define RXCTL_IA1 (1 << 1)
-#define RXCTL_IA0 (1 << 0)
-
-#define TXCTL_DEFDIS (1 << 7)
-#define TXCTL_MBE (1 << 6)
-#define TXCTL_ICRC (1 << 5)
-#define TXCTL_TPD (1 << 4)
-#define TXCTL_OCOLL (1 << 3)
-#define TXCTL_SP (1 << 2)
-#define TXCTL_PB (1 << 1)
-#define TXCTL_STXON (1 << 0)
-
-#define MIICMD_REGAD_MASK (0x001F)
-#define MIICMD_PHYAD_MASK (0x03E0)
-#define MIICMD_OPCODE_MASK (0xC000)
-#define MIICMD_PHYAD_8950 (0x0000)
-#define MIICMD_OPCODE_READ (0x8000)
-#define MIICMD_OPCODE_WRITE (0x4000)
-
-#define MIISTS_BUSY (1 << 0)
-
-/*
- * 0x80020000 - 0x8002FFFF: USB OHCI
- */
-#define USB_OFFSET 0x020000
-#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
-
-/*
- * 0x80030000 - 0x8003FFFF: Raster engine
- */
-#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
-#define RASTER_OFFSET 0x030000
-#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
-#endif
-
-/*
- * 0x80040000 - 0x8004FFFF: Graphics accelerator
- */
-#if defined(CONFIG_EP9315)
-#define GFX_OFFSET 0x040000
-#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
-#endif
-
-/*
- * 0x80050000 - 0x8005FFFF: Reserved
- */
-
-/*
- * 0x80060000 - 0x8006FFFF: SDRAM controller
- */
-#define SDRAM_OFFSET 0x060000
-#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct sdram_regs {
- uint32_t reserved;
- uint32_t glconfig;
- uint32_t refrshtimr;
- uint32_t bootsts;
- uint32_t devcfg0;
- uint32_t devcfg1;
- uint32_t devcfg2;
- uint32_t devcfg3;
-};
-#endif
-
-#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
-#define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
-#define SDRAM_DEVCFG_SROMLL (1 << 5)
-#define SDRAM_DEVCFG_CASLAT_2 0x00010000
-#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
-
-#define SDRAM_OFF_GLCONFIG 0x0004
-#define SDRAM_OFF_REFRSHTIMR 0x0008
-
-#define SDRAM_OFF_DEVCFG0 0x0010
-#define SDRAM_OFF_DEVCFG1 0x0014
-#define SDRAM_OFF_DEVCFG2 0x0018
-#define SDRAM_OFF_DEVCFG3 0x001C
-
-#define SDRAM_DEVCFG0_BASE 0xC0000000
-#define SDRAM_DEVCFG1_BASE 0xD0000000
-#define SDRAM_DEVCFG2_BASE 0xE0000000
-#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
-#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
-
-#define GLCONFIG_INIT (1 << 0)
-#define GLCONFIG_MRS (1 << 1)
-#define GLCONFIG_SMEMBUSY (1 << 5)
-#define GLCONFIG_LCR (1 << 6)
-#define GLCONFIG_REARBEN (1 << 7)
-#define GLCONFIG_CLKSHUTDOWN (1 << 30)
-#define GLCONFIG_CKE (1 << 31)
-
-#define EP93XX_SDRAMCTRL 0x80060000
-#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
-#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
-#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
-#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
-#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
-#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
-#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
-
-#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
-
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
-#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
-
-#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
-#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
-#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
-#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
-#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
-#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
-#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
-#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
-#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
-#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
-#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
-#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
-
-/*
- * 0x80070000 - 0x8007FFFF: Reserved
- */
-
-/*
- * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
- */
-#define SMC_OFFSET 0x080000
-#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct smc_regs {
- uint32_t bcr0;
- uint32_t bcr1;
- uint32_t bcr2;
- uint32_t bcr3;
- uint32_t reserved0[2];
- uint32_t bcr6;
- uint32_t bcr7;
-#if defined(CONFIG_EP9315)
- uint32_t pcattribute;
- uint32_t pccommon;
- uint32_t pcio;
- uint32_t reserved1[5];
- uint32_t pcmciactrl;
-#endif
-};
-#endif
-
-#define EP93XX_OFF_SMCBCR0 0x00
-#define EP93XX_OFF_SMCBCR1 0x04
-#define EP93XX_OFF_SMCBCR2 0x08
-#define EP93XX_OFF_SMCBCR3 0x0C
-#define EP93XX_OFF_SMCBCR6 0x18
-#define EP93XX_OFF_SMCBCR7 0x1C
-
-#define SMC_BCR_IDCY_SHIFT 0
-#define SMC_BCR_WST1_SHIFT 5
-#define SMC_BCR_BLE (1 << 10)
-#define SMC_BCR_WST2_SHIFT 11
-#define SMC_BCR_MW_SHIFT 28
-
-/*
- * 0x80090000 - 0x8009FFFF: Boot ROM
- */
-
-/*
- * 0x800A0000 - 0x800AFFFF: IDE interface
- */
-
-/*
- * 0x800B0000 - 0x800BFFFF: VIC1
- */
-
-/*
- * 0x800C0000 - 0x800CFFFF: VIC2
- */
-
-/*
- * 0x800D0000 - 0x800FFFFF: Reserved
- */
-
-/*
- * 0x80800000 - 0x8080FFFF: Reserved
- */
-
-/*
- * 0x80810000 - 0x8081FFFF: Timers
- */
-#define TIMER_OFFSET 0x010000
-#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct timer {
- uint32_t load;
- uint32_t value;
- uint32_t control;
- uint32_t clear;
-};
-
-struct timer4 {
- uint32_t value_low;
- uint32_t value_high;
-};
-
-struct timer_regs {
- struct timer timer1;
- uint32_t reserved0[4];
- struct timer timer2;
- uint32_t reserved1[12];
- struct timer4 timer4;
- uint32_t reserved2[6];
- struct timer timer3;
-};
-#endif
-
-/*
- * 0x80820000 - 0x8082FFFF: I2S
- */
-#define I2S_OFFSET 0x020000
-#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
-
-/*
- * 0x80830000 - 0x8083FFFF: Security
- */
-#define SECURITY_OFFSET 0x030000
-#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
-
-#define EXTENSIONID (SECURITY_BASE + 0x2714)
-
-/*
- * 0x80840000 - 0x8084FFFF: GPIO
- */
-#define GPIO_OFFSET 0x040000
-#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct gpio_int {
- uint32_t inttype1;
- uint32_t inttype2;
- uint32_t eoi;
- uint32_t inten;
- uint32_t intsts;
- uint32_t rawintsts;
- uint32_t db;
-};
-
-struct gpio_regs {
- uint32_t padr;
- uint32_t pbdr;
- uint32_t pcdr;
- uint32_t pddr;
- uint32_t paddr;
- uint32_t pbddr;
- uint32_t pcddr;
- uint32_t pdddr;
- uint32_t pedr;
- uint32_t peddr;
- uint32_t reserved0[2];
- uint32_t pfdr;
- uint32_t pfddr;
- uint32_t pgdr;
- uint32_t pgddr;
- uint32_t phdr;
- uint32_t phddr;
- uint32_t reserved1;
- uint32_t finttype1;
- uint32_t finttype2;
- uint32_t reserved2;
- struct gpio_int pfint;
- uint32_t reserved3[10];
- struct gpio_int paint;
- struct gpio_int pbint;
- uint32_t eedrive;
-};
-#endif
-
-#define EP93XX_LED_DATA 0x80840020
-#define EP93XX_LED_GREEN_ON 0x0001
-#define EP93XX_LED_RED_ON 0x0002
-
-#define EP93XX_LED_DDR 0x80840024
-#define EP93XX_LED_GREEN_ENABLE 0x0001
-#define EP93XX_LED_RED_ENABLE 0x00020000
-
-/*
- * 0x80850000 - 0x8087FFFF: Reserved
- */
-
-/*
- * 0x80880000 - 0x8088FFFF: AAC
- */
-#define AAC_OFFSET 0x080000
-#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
-
-/*
- * 0x80890000 - 0x8089FFFF: Reserved
- */
-
-/*
- * 0x808A0000 - 0x808AFFFF: SPI
- */
-#define SPI_OFFSET 0x0A0000
-#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
-
-/*
- * 0x808B0000 - 0x808BFFFF: IrDA
- */
-#define IRDA_OFFSET 0x0B0000
-#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
-
-/*
- * 0x808C0000 - 0x808CFFFF: UART1
- */
-#define UART1_OFFSET 0x0C0000
-#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
-
-/*
- * 0x808D0000 - 0x808DFFFF: UART2
- */
-#define UART2_OFFSET 0x0D0000
-#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
-
-/*
- * 0x808E0000 - 0x808EFFFF: UART3
- */
-#define UART3_OFFSET 0x0E0000
-#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
-
-/*
- * 0x808F0000 - 0x808FFFFF: Key Matrix
- */
-#define KEY_OFFSET 0x0F0000
-#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
-
-/*
- * 0x80900000 - 0x8090FFFF: Touchscreen
- */
-#define TOUCH_OFFSET 0x900000
-#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
-
-/*
- * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
- */
-#define PWM_OFFSET 0x910000
-#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
-
-/*
- * 0x80920000 - 0x8092FFFF: Real time clock
- */
-#define RTC_OFFSET 0x920000
-#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
-
-/*
- * 0x80930000 - 0x8093FFFF: Syscon
- */
-#define SYSCON_OFFSET 0x930000
-#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
-
-/* Security */
-#define SECURITY_EXTENSIONID 0x80832714
-
-#ifndef __ASSEMBLY__
-struct syscon_regs {
- uint32_t pwrsts;
- uint32_t pwrcnt;
- uint32_t halt;
- uint32_t stby;
- uint32_t reserved0[2];
- uint32_t teoi;
- uint32_t stfclr;
- uint32_t clkset1;
- uint32_t clkset2;
- uint32_t reserved1[6];
- uint32_t scratch0;
- uint32_t scratch1;
- uint32_t reserved2[2];
- uint32_t apbwait;
- uint32_t bustmstrarb;
- uint32_t bootmodeclr;
- uint32_t reserved3[9];
- uint32_t devicecfg;
- uint32_t vidclkdiv;
- uint32_t mirclkdiv;
- uint32_t i2sclkdiv;
- uint32_t keytchclkdiv;
- uint32_t chipid;
- uint32_t reserved4;
- uint32_t syscfg;
- uint32_t reserved5[8];
- uint32_t sysswlock;
-};
-#else
-#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
-#endif
-
-#define SYSCON_OFF_CLKSET1 0x0020
-#define SYSCON_OFF_SYSCFG 0x009c
-
-#define SYSCON_PWRCNT_UART_BAUD (1 << 29)
-#define SYSCON_PWRCNT_USH_EN (1 << 28)
-
-#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
-#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
-#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
-#define SYSCON_CLKSET_PLL_PS_SHIFT 16
-#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
-#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
-#define SYSCON_CLKSET1_NBYP1 (1 << 23)
-#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
-
-#define SYSCON_CLKSET2_PLL2_EN (1 << 18)
-#define SYSCON_CLKSET2_NBYP2 (1 << 19)
-#define SYSCON_CLKSET2_USB_DIV_SHIFT 28
-
-#define SYSCON_CHIPID_REV_MASK 0xF0000000
-#define SYSCON_DEVICECFG_SWRST (1 << 31)
-
-#define SYSCON_SYSCFG_LASDO 0x00000020
-
-/*
- * 0x80930000 - 0x8093FFFF: Watchdog Timer
- */
-#define WATCHDOG_OFFSET 0x940000
-#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
-
-/*
- * 0x80950000 - 0x9000FFFF: Reserved
- */
-
-/*
- * During low_level init we store memory layout in memory at specific location
- */
-#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
-#define UBOOT_MEMORYCNF_BANK_MASK 0x2004
-#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 69570bebb447..16733d2d1f8b 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -22,7 +22,6 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
-obj-$(CONFIG_EP93XX) += ep93xx_eth.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c
deleted file mode 100644
index 9f8df7de0609..000000000000
--- a/drivers/net/ep93xx_eth.c
+++ /dev/null
@@ -1,654 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Cirrus Logic EP93xx ethernet MAC / MII driver.
- *
- * Copyright (C) 2010, 2009
- * Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
- * which is
- *
- * (C) Copyright 2002 2003
- * Adam Bezanson, Network Audio Technologies, Inc.
- * <bezanson@netaudiotech.com>
- */
-
-#include <command.h>
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <linux/bug.h>
-#include <linux/types.h>
-#include "ep93xx_eth.h"
-
-#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
-#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
-
-/* ep93xx_miiphy ops forward declarations */
-static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad,
- int reg);
-static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad,
- int reg, u16 value);
-
-#if defined(EP93XX_MAC_DEBUG)
-/**
- * Dump ep93xx_mac values to the terminal.
- */
-static void dump_dev(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_dev()\n");
- printf(" rx_dq.base %p\n", priv->rx_dq.base);
- printf(" rx_dq.current %p\n", priv->rx_dq.current);
- printf(" rx_dq.end %p\n", priv->rx_dq.end);
- printf(" rx_sq.base %p\n", priv->rx_sq.base);
- printf(" rx_sq.current %p\n", priv->rx_sq.current);
- printf(" rx_sq.end %p\n", priv->rx_sq.end);
-
- for (i = 0; i < NUMRXDESC; i++)
- printf(" rx_buffer[%2.d] %p\n", i, net_rx_packets[i]);
-
- printf(" tx_dq.base %p\n", priv->tx_dq.base);
- printf(" tx_dq.current %p\n", priv->tx_dq.current);
- printf(" tx_dq.end %p\n", priv->tx_dq.end);
- printf(" tx_sq.base %p\n", priv->tx_sq.base);
- printf(" tx_sq.current %p\n", priv->tx_sq.current);
- printf(" tx_sq.end %p\n", priv->tx_sq.end);
-}
-
-/**
- * Dump all RX status queue entries to the terminal.
- */
-static void dump_rx_status_queue(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_rx_status_queue()\n");
- printf(" descriptor address word1 word2\n");
- for (i = 0; i < NUMRXDESC; i++) {
- printf(" [ %p ] %08X %08X\n",
- priv->rx_sq.base + i,
- (priv->rx_sq.base + i)->word1,
- (priv->rx_sq.base + i)->word2);
- }
-}
-
-/**
- * Dump all RX descriptor queue entries to the terminal.
- */
-static void dump_rx_descriptor_queue(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_rx_descriptor_queue()\n");
- printf(" descriptor address word1 word2\n");
- for (i = 0; i < NUMRXDESC; i++) {
- printf(" [ %p ] %08X %08X\n",
- priv->rx_dq.base + i,
- (priv->rx_dq.base + i)->word1,
- (priv->rx_dq.base + i)->word2);
- }
-}
-
-/**
- * Dump all TX descriptor queue entries to the terminal.
- */
-static void dump_tx_descriptor_queue(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_tx_descriptor_queue()\n");
- printf(" descriptor address word1 word2\n");
- for (i = 0; i < NUMTXDESC; i++) {
- printf(" [ %p ] %08X %08X\n",
- priv->tx_dq.base + i,
- (priv->tx_dq.base + i)->word1,
- (priv->tx_dq.base + i)->word2);
- }
-}
-
-/**
- * Dump all TX status queue entries to the terminal.
- */
-static void dump_tx_status_queue(struct eth_device *dev)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int i;
-
- printf("\ndump_tx_status_queue()\n");
- printf(" descriptor address word1\n");
- for (i = 0; i < NUMTXDESC; i++) {
- printf(" [ %p ] %08X\n",
- priv->rx_sq.base + i,
- (priv->rx_sq.base + i)->word1);
- }
-}
-#else
-#define dump_dev(x)
-#define dump_rx_descriptor_queue(x)
-#define dump_rx_status_queue(x)
-#define dump_tx_descriptor_queue(x)
-#define dump_tx_status_queue(x)
-#endif /* defined(EP93XX_MAC_DEBUG) */
-
-/**
- * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
- * it's cleared.
- */
-static void ep93xx_mac_reset(struct eth_device *dev)
-{
- struct mac_regs *mac = GET_REGS(dev);
- uint32_t value;
-
- debug("+ep93xx_mac_reset");
-
- value = readl(&mac->selfctl);
- value |= SELFCTL_RESET;
- writel(value, &mac->selfctl);
-
- while (readl(&mac->selfctl) & SELFCTL_RESET)
- ; /* noop */
-
- debug("-ep93xx_mac_reset");
-}
-
-/* Eth device open */
-static int ep93xx_eth_open(struct eth_device *dev, struct bd_info *bd)
-{
- struct ep93xx_priv *priv = GET_PRIV(dev);
- struct mac_regs *mac = GET_REGS(dev);
- uchar *mac_addr = dev->enetaddr;
- int i;
-
- debug("+ep93xx_eth_open");
-
- /* Reset the MAC */
- ep93xx_mac_reset(dev);
-
- /* Reset the descriptor queues' current and end address values */
- priv->tx_dq.current = priv->tx_dq.base;
- priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
-
- priv->tx_sq.current = priv->tx_sq.base;
- priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
-
- priv->rx_dq.current = priv->rx_dq.base;
- priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
-
- priv->rx_sq.current = priv->rx_sq.base;
- priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
-
- /*
- * Set the transmit descriptor and status queues' base address,
- * current address, and length registers. Set the maximum frame
- * length and threshold. Enable the transmit descriptor processor.
- */
- writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
- writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
- writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
-
- writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
- writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
- writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
-
- writel(0x00040000, &mac->txdthrshld);
- writel(0x00040000, &mac->txststhrshld);
-
- writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
- writel(BMCTL_TXEN, &mac->bmctl);
-
- /*
- * Set the receive descriptor and status queues' base address,
- * current address, and length registers. Enable the receive
- * descriptor processor.
- */
- writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
- writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
- writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
-
- writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
- writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
- writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
-
- writel(0x00040000, &mac->rxdthrshld);
-
- writel(BMCTL_RXEN, &mac->bmctl);
-
- writel(0x00040000, &mac->rxststhrshld);
-
- /* Wait until the receive descriptor processor is active */
- while (!(readl(&mac->bmsts) & BMSTS_RXACT))
- ; /* noop */
-
- /*
- * Initialize the RX descriptor queue. Clear the TX descriptor queue.
- * Clear the RX and TX status queues. Enqueue the RX descriptor and
- * status entries to the MAC.
- */
- for (i = 0; i < NUMRXDESC; i++) {
- /* set buffer address */
- (priv->rx_dq.base + i)->word1 = (uint32_t)net_rx_packets[i];
-
- /* set buffer length, clear buffer index and NSOF */
- (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
- }
-
- memset(priv->tx_dq.base, 0,
- (sizeof(struct tx_descriptor) * NUMTXDESC));
- memset(priv->rx_sq.base, 0,
- (sizeof(struct rx_status) * NUMRXDESC));
- memset(priv->tx_sq.base, 0,
- (sizeof(struct tx_status) * NUMTXDESC));
-
- writel(NUMRXDESC, &mac->rxdqenq);
- writel(NUMRXDESC, &mac->rxstsqenq);
-
- /* Set the primary MAC address */
- writel(AFP_IAPRIMARY, &mac->afp);
- writel(mac_addr[0] | (mac_addr[1] << 8) |
- (mac_addr[2] << 16) | (mac_addr[3] << 24),
- &mac->indad);
- writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
-
- /* Turn on RX and TX */
- writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
- RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
- writel(TXCTL_STXON, &mac->txctl);
-
- /* Dump data structures if we're debugging */
- dump_dev(dev);
- dump_rx_descriptor_queue(dev);
- dump_rx_status_queue(dev);
- dump_tx_descriptor_queue(dev);
- dump_tx_status_queue(dev);
-
- debug("-ep93xx_eth_open");
-
- return 1;
-}
-
-/**
- * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
- * registers.
- */
-static void ep93xx_eth_close(struct eth_device *dev)
-{
- struct mac_regs *mac = GET_REGS(dev);
-
- debug("+ep93xx_eth_close");
-
- writel(0x00000000, &mac->rxctl);
- writel(0x00000000, &mac->txctl);
-
- debug("-ep93xx_eth_close");
-}
-
-/**
- * Copy a frame of data from the MAC into the protocol layer for further
- * processing.
- */
-static int ep93xx_eth_rcv_packet(struct eth_device *dev)
-{
- struct mac_regs *mac = GET_REGS(dev);
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int len = -1;
-
- debug("+ep93xx_eth_rcv_packet");
-
- if (RX_STATUS_RFP(priv->rx_sq.current)) {
- if (RX_STATUS_RWE(priv->rx_sq.current)) {
- /*
- * We have a good frame. Extract the frame's length
- * from the current rx_status_queue entry, and copy
- * the frame's data into net_rx_packets[] of the
- * protocol stack. We track the total number of
- * bytes in the frame (nbytes_frame) which will be
- * used when we pass the data off to the protocol
- * layer via net_process_received_packet().
- */
- len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
-
- net_process_received_packet(
- (uchar *)priv->rx_dq.current->word1, len);
-
- debug("reporting %d bytes...\n", len);
- } else {
- /* Do we have an erroneous packet? */
- pr_err("packet rx error, status %08X %08X",
- priv->rx_sq.current->word1,
- priv->rx_sq.current->word2);
- dump_rx_descriptor_queue(dev);
- dump_rx_status_queue(dev);
- }
-
- /*
- * Clear the associated status queue entry, and
- * increment our current pointers to the next RX
- * descriptor and status queue entries (making sure
- * we wrap properly).
- */
- memset((void *)priv->rx_sq.current, 0,
- sizeof(struct rx_status));
-
- priv->rx_sq.current++;
- if (priv->rx_sq.current >= priv->rx_sq.end)
- priv->rx_sq.current = priv->rx_sq.base;
-
- priv->rx_dq.current++;
- if (priv->rx_dq.current >= priv->rx_dq.end)
- priv->rx_dq.current = priv->rx_dq.base;
-
- /*
- * Finally, return the RX descriptor and status entries
- * back to the MAC engine, and loop again, checking for
- * more descriptors to process.
- */
- writel(1, &mac->rxdqenq);
- writel(1, &mac->rxstsqenq);
- } else {
- len = 0;
- }
-
- debug("-ep93xx_eth_rcv_packet %d", len);
- return len;
-}
-
-/**
- * Send a block of data via ethernet.
- */
-static int ep93xx_eth_send_packet(struct eth_device *dev,
- void * const packet, int const length)
-{
- struct mac_regs *mac = GET_REGS(dev);
- struct ep93xx_priv *priv = GET_PRIV(dev);
- int ret = -1;
-
- debug("+ep93xx_eth_send_packet");
-
- /* Parameter check */
- BUG_ON(packet == NULL);
-
- /*
- * Initialize the TX descriptor queue with the new packet's info.
- * Clear the associated status queue entry. Enqueue the packet
- * to the MAC for transmission.
- */
-
- /* set buffer address */
- priv->tx_dq.current->word1 = (uint32_t)packet;
-
- /* set buffer length and EOF bit */
- priv->tx_dq.current->word2 = length | TX_DESC_EOF;
-
- /* clear tx status */
- priv->tx_sq.current->word1 = 0;
-
- /* enqueue the TX descriptor */
- writel(1, &mac->txdqenq);
-
- /* wait for the frame to become processed */
- while (!TX_STATUS_TXFP(priv->tx_sq.current))
- ; /* noop */
-
- if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
- pr_err("packet tx error, status %08X",
- priv->tx_sq.current->word1);
- dump_tx_descriptor_queue(dev);
- dump_tx_status_queue(dev);
-
- /* TODO: Add better error handling? */
- goto eth_send_out;
- }
-
- ret = 0;
- /* Fall through */
-
-eth_send_out:
- debug("-ep93xx_eth_send_packet %d", ret);
- return ret;
-}
-
-#if defined(CONFIG_MII)
-int ep93xx_miiphy_initialize(struct bd_info * const bd)
-{
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
- mdiodev->read = ep93xx_miiphy_read;
- mdiodev->write = ep93xx_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
- return 0;
-}
-#endif
-
-/**
- * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
- * allocated, if necessary, for the TX and RX descriptor and status queues,
- * as well as for received packets. The EP93XX MAC hardware is initialized.
- * Transmit and receive operations are enabled.
- */
-int ep93xx_eth_initialize(u8 dev_num, int base_addr)
-{
- int ret = -1;
- struct eth_device *dev;
- struct ep93xx_priv *priv;
-
- debug("+ep93xx_eth_initialize");
-
- priv = malloc(sizeof(*priv));
- if (!priv) {
- pr_err("malloc() failed");
- goto eth_init_failed_0;
- }
- memset(priv, 0, sizeof(*priv));
-
- priv->regs = (struct mac_regs *)base_addr;
-
- priv->tx_dq.base = calloc(NUMTXDESC,
- sizeof(struct tx_descriptor));
- if (priv->tx_dq.base == NULL) {
- pr_err("calloc() failed");
- goto eth_init_failed_1;
- }
-
- priv->tx_sq.base = calloc(NUMTXDESC,
- sizeof(struct tx_status));
- if (priv->tx_sq.base == NULL) {
- pr_err("calloc() failed");
- goto eth_init_failed_2;
- }
-
- priv->rx_dq.base = calloc(NUMRXDESC,
- sizeof(struct rx_descriptor));
- if (priv->rx_dq.base == NULL) {
- pr_err("calloc() failed");
- goto eth_init_failed_3;
- }
-
- priv->rx_sq.base = calloc(NUMRXDESC,
- sizeof(struct rx_status));
- if (priv->rx_sq.base == NULL) {
- pr_err("calloc() failed");
- goto eth_init_failed_4;
- }
-
- dev = malloc(sizeof *dev);
- if (dev == NULL) {
- pr_err("malloc() failed");
- goto eth_init_failed_5;
- }
- memset(dev, 0, sizeof *dev);
-
- dev->iobase = base_addr;
- dev->priv = priv;
- dev->init = ep93xx_eth_open;
- dev->halt = ep93xx_eth_close;
- dev->send = ep93xx_eth_send_packet;
- dev->recv = ep93xx_eth_rcv_packet;
-
- sprintf(dev->name, "ep93xx_eth-%hu", dev_num);
-
- eth_register(dev);
-
- /* Done! */
- ret = 1;
- goto eth_init_done;
-
-eth_init_failed_5:
- free(priv->rx_sq.base);
- /* Fall through */
-
-eth_init_failed_4:
- free(priv->rx_dq.base);
- /* Fall through */
-
-eth_init_failed_3:
- free(priv->tx_sq.base);
- /* Fall through */
-
-eth_init_failed_2:
- free(priv->tx_dq.base);
- /* Fall through */
-
-eth_init_failed_1:
- free(priv);
- /* Fall through */
-
-eth_init_failed_0:
- /* Fall through */
-
-eth_init_done:
- debug("-ep93xx_eth_initialize %d", ret);
- return ret;
-}
-
-#if defined(CONFIG_MII)
-
-/**
- * Maximum MII address we support
- */
-#define MII_ADDRESS_MAX 31
-
-/**
- * Maximum MII register address we support
- */
-#define MII_REGISTER_MAX 31
-
-/**
- * Read a 16-bit value from an MII register.
- */
-static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad,
- int reg)
-{
- unsigned short value = 0;
- struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
- int ret = -1;
- uint32_t self_ctl;
-
- debug("+ep93xx_miiphy_read");
-
- /* Parameter checks */
- BUG_ON(bus->name == NULL);
- BUG_ON(addr > MII_ADDRESS_MAX);
- BUG_ON(reg > MII_REGISTER_MAX);
-
- /*
- * Save the current SelfCTL register value. Set MAC to suppress
- * preamble bits. Wait for any previous MII command to complete
- * before issuing the new command.
- */
- self_ctl = readl(&mac->selfctl);
-#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
- writel(self_ctl & ~(1 << 8), &mac->selfctl);
-#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
-
- while (readl(&mac->miists) & MIISTS_BUSY)
- ; /* noop */
-
- /*
- * Issue the MII 'read' command. Wait for the command to complete.
- * Read the MII data value.
- */
- writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
- &mac->miicmd);
- while (readl(&mac->miists) & MIISTS_BUSY)
- ; /* noop */
-
- value = (unsigned short)readl(&mac->miidata);
-
- /* Restore the saved SelfCTL value and return. */
- writel(self_ctl, &mac->selfctl);
-
- ret = 0;
- /* Fall through */
-
- debug("-ep93xx_miiphy_read");
- if (ret < 0)
- return ret;
- return value;
-}
-
-/**
- * Write a 16-bit value to an MII register.
- */
-static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad,
- int reg, u16 value)
-{
- struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
- int ret = -1;
- uint32_t self_ctl;
-
- debug("+ep93xx_miiphy_write");
-
- /* Parameter checks */
- BUG_ON(bus->name == NULL);
- BUG_ON(addr > MII_ADDRESS_MAX);
- BUG_ON(reg > MII_REGISTER_MAX);
-
- /*
- * Save the current SelfCTL register value. Set MAC to suppress
- * preamble bits. Wait for any previous MII command to complete
- * before issuing the new command.
- */
- self_ctl = readl(&mac->selfctl);
-#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
- writel(self_ctl & ~(1 << 8), &mac->selfctl);
-#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
-
- while (readl(&mac->miists) & MIISTS_BUSY)
- ; /* noop */
-
- /* Issue the MII 'write' command. Wait for the command to complete. */
- writel((uint32_t)value, &mac->miidata);
- writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
- &mac->miicmd);
- while (readl(&mac->miists) & MIISTS_BUSY)
- ; /* noop */
-
- /* Restore the saved SelfCTL value and return. */
- writel(self_ctl, &mac->selfctl);
-
- ret = 0;
- /* Fall through */
-
- debug("-ep93xx_miiphy_write");
- return ret;
-}
-#endif /* defined(CONFIG_MII) */
diff --git a/drivers/net/ep93xx_eth.h b/drivers/net/ep93xx_eth.h
deleted file mode 100644
index 074fe25f347c..000000000000
--- a/drivers/net/ep93xx_eth.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- */
-
-#ifndef _EP93XX_ETH_H
-#define _EP93XX_ETH_H
-
-#include <net.h>
-
-/**
- * #define this to dump device status and queue info during initialization and
- * following errors.
- */
-#undef EP93XX_MAC_DEBUG
-
-/**
- * Number of descriptor and status entries in our RX queues.
- * It must be power of 2 !
- */
-#define NUMRXDESC PKTBUFSRX
-
-/**
- * Number of descriptor and status entries in our TX queues.
- */
-#define NUMTXDESC 1
-
-/**
- * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
- */
-#define TXSTARTMAX 944
-
-/**
- * Receive descriptor queue entry
- */
-struct rx_descriptor {
- uint32_t word1;
- uint32_t word2;
-};
-
-/**
- * Receive status queue entry
- */
-struct rx_status {
- uint32_t word1;
- uint32_t word2;
-};
-
-#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
-#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
-#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
-
-/**
- * Transmit descriptor queue entry
- */
-struct tx_descriptor {
- uint32_t word1;
- uint32_t word2;
-};
-
-#define TX_DESC_EOF (1 << 31)
-
-/**
- * Transmit status queue entry
- */
-struct tx_status {
- uint32_t word1;
-};
-
-#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
-#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
-
-/**
- * Transmit descriptor queue
- */
-struct tx_descriptor_queue {
- struct tx_descriptor *base;
- struct tx_descriptor *current;
- struct tx_descriptor *end;
-};
-
-/**
- * Transmit status queue
- */
-struct tx_status_queue {
- struct tx_status *base;
- volatile struct tx_status *current;
- struct tx_status *end;
-};
-
-/**
- * Receive descriptor queue
- */
-struct rx_descriptor_queue {
- struct rx_descriptor *base;
- struct rx_descriptor *current;
- struct rx_descriptor *end;
-};
-
-/**
- * Receive status queue
- */
-struct rx_status_queue {
- struct rx_status *base;
- volatile struct rx_status *current;
- struct rx_status *end;
-};
-
-/**
- * EP93xx MAC private data structure
- */
-struct ep93xx_priv {
- struct rx_descriptor_queue rx_dq;
- struct rx_status_queue rx_sq;
- void *rx_buffer[NUMRXDESC];
-
- struct tx_descriptor_queue tx_dq;
- struct tx_status_queue tx_sq;
-
- struct mac_regs *regs;
-};
-
-#endif
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index eb6fe9f6b30f..a4472da9f182 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_USB_ATMEL) += ohci-at91.o
obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
-obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
obj-$(CONFIG_USB_OHCI_PCI) += ohci-pci.o
obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
diff --git a/drivers/usb/host/ohci-ep93xx.c b/drivers/usb/host/ohci-ep93xx.c
deleted file mode 100644
index 9654fa2996f8..000000000000
--- a/drivers/usb/host/ohci-ep93xx.c
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013
- * Sergey Kostanbaev < sergey.kostanbaev <at> fairwaves.ru >
- */
-
-#include <config.h>
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-#include <asm/io.h>
-#include <asm/arch/ep93xx.h>
-
-int usb_cpu_init(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- unsigned long pwr = readl(&syscon->pwrcnt);
- writel(pwr | SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
-
- return 0;
-}
-
-int usb_cpu_stop(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- unsigned long pwr = readl(&syscon->pwrcnt);
- writel(pwr & ~SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
-
- return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
- return usb_cpu_stop();
-}
-
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 01/10] net: Remove armada100_fec driver
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
` (8 preceding siblings ...)
2022-03-31 17:46 ` [PATCH 10/10] arm: Remove unused ep93xx code Tom Rini
@ 2022-04-08 18:04 ` Tom Rini
9 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:04 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 245 bytes --]
On Thu, Mar 31, 2022 at 01:46:44PM -0400, Tom Rini wrote:
> This driver is not enabled by any board and not converted to DM_ETH.
> Remove.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 02/10] net: Remove ax88180 driver
2022-03-31 17:46 ` [PATCH 02/10] net: Remove ax88180 driver Tom Rini
@ 2022-04-08 18:04 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:04 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 245 bytes --]
On Thu, Mar 31, 2022 at 01:46:45PM -0400, Tom Rini wrote:
> This driver is not enabled by any board and not converted to DM_ETH.
> Remove.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 03/10] net: Remove cs8900 driver
2022-03-31 17:46 ` [PATCH 03/10] net: Remove cs8900 driver Tom Rini
@ 2022-04-08 18:04 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:04 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 245 bytes --]
On Thu, Mar 31, 2022 at 01:46:46PM -0400, Tom Rini wrote:
> This driver is not enabled by any board and not converted to DM_ETH.
> Remove.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 04/10] net: Remove dnet driver
2022-03-31 17:46 ` [PATCH 04/10] net: Remove dnet driver Tom Rini
@ 2022-04-08 18:05 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:05 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 245 bytes --]
On Thu, Mar 31, 2022 at 01:46:47PM -0400, Tom Rini wrote:
> This driver is not enabled by any board and not converted to DM_ETH.
> Remove.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 05/10] net: Remove ftmac110 driver
2022-03-31 17:46 ` [PATCH 05/10] net: Remove ftmac110 driver Tom Rini
@ 2022-04-08 18:05 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:05 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 245 bytes --]
On Thu, Mar 31, 2022 at 01:46:48PM -0400, Tom Rini wrote:
> This driver is not enabled by any board and not converted to DM_ETH.
> Remove.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 06/10] net: Remove lan91c96 driver
2022-03-31 17:46 ` [PATCH 06/10] net: Remove lan91c96 driver Tom Rini
@ 2022-04-08 18:05 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:05 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 245 bytes --]
On Thu, Mar 31, 2022 at 01:46:49PM -0400, Tom Rini wrote:
> This driver is not enabled by any board and not converted to DM_ETH.
> Remove.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 07/10] net: Remove natsemi driver
2022-03-31 17:46 ` [PATCH 07/10] net: Remove natsemi driver Tom Rini
@ 2022-04-08 18:05 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:05 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 245 bytes --]
On Thu, Mar 31, 2022 at 01:46:50PM -0400, Tom Rini wrote:
> This driver is not enabled by any board and not converted to DM_ETH.
> Remove.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 08/10] net: Remove ns8382x driver
2022-03-31 17:46 ` [PATCH 08/10] net: Remove ns8382x driver Tom Rini
@ 2022-04-08 18:05 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:05 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 245 bytes --]
On Thu, Mar 31, 2022 at 01:46:51PM -0400, Tom Rini wrote:
> This driver is not enabled by any board and not converted to DM_ETH.
> Remove.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 09/10] net: Remove uli526x driver
2022-03-31 17:46 ` [PATCH 09/10] net: Remove uli526x driver Tom Rini
@ 2022-04-08 18:05 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:05 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 245 bytes --]
On Thu, Mar 31, 2022 at 01:46:52PM -0400, Tom Rini wrote:
> This driver is not enabled by any board and not converted to DM_ETH.
> Remove.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 10/10] arm: Remove unused ep93xx code
2022-03-31 17:46 ` [PATCH 10/10] arm: Remove unused ep93xx code Tom Rini
@ 2022-04-08 18:05 ` Tom Rini
0 siblings, 0 replies; 20+ messages in thread
From: Tom Rini @ 2022-04-08 18:05 UTC (permalink / raw)
To: u-boot
[-- Attachment #1: Type: text/plain, Size: 242 bytes --]
On Thu, Mar 31, 2022 at 01:46:53PM -0400, Tom Rini wrote:
> There are no platforms for this architecture anymore, remove unused
> code.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-04-08 18:08 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-03-31 17:46 [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
2022-03-31 17:46 ` [PATCH 02/10] net: Remove ax88180 driver Tom Rini
2022-04-08 18:04 ` Tom Rini
2022-03-31 17:46 ` [PATCH 03/10] net: Remove cs8900 driver Tom Rini
2022-04-08 18:04 ` Tom Rini
2022-03-31 17:46 ` [PATCH 04/10] net: Remove dnet driver Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 05/10] net: Remove ftmac110 driver Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 06/10] net: Remove lan91c96 driver Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 07/10] net: Remove natsemi driver Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 08/10] net: Remove ns8382x driver Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 09/10] net: Remove uli526x driver Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-03-31 17:46 ` [PATCH 10/10] arm: Remove unused ep93xx code Tom Rini
2022-04-08 18:05 ` Tom Rini
2022-04-08 18:04 ` [PATCH 01/10] net: Remove armada100_fec driver Tom Rini
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