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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id t14-20020a170906608e00b006d1455acc62sm10004538ejj.74.2022.04.09.09.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 09:55:30 -0700 (PDT) From: Johan Jonker To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, heiko@sntech.de, peng.fan@nxp.com, jh80.chung@samsung.com, u-boot@lists.denx.de Subject: [PATCH v5 07/13] rockchip: mmc: rockchip_dw_mmc: fix ciu clock index Date: Sat, 9 Apr 2022 18:55:08 +0200 Message-Id: <20220409165514.19220-8-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220409165514.19220-1-jbx6244@gmail.com> References: <20220409165514.19220-1-jbx6244@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The document rockchip-dw-mshc.yaml decribes a maximum of 4 clocks. In the rockchip_dw_mmc driver the clock name in use was "fixed" to "ciu" with index 1, but later reverted back to index 0. The clock drivers can handle both, but the calling driver should submit correct data as a standard practice. Fix the "ciu" clock index by setting it back to 1. clock-names: minItems: 2 items: - const: biu - const: ciu - const: ciu-drive - const: ciu-sample Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/mmc/rockchip_dw_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 7f8dea1e34..be065ec0c3 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -123,11 +123,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev) priv->minmax[0] = 400000; /* 400 kHz */ priv->minmax[1] = dtplat->max_frequency; - ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); + ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk); if (ret < 0) return ret; #else - ret = clk_get_by_index(dev, 0, &priv->clk); + ret = clk_get_by_index(dev, 1, &priv->clk); if (ret < 0) return ret; #endif -- 2.20.1