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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id t14-20020a170906608e00b006d1455acc62sm10004538ejj.74.2022.04.09.09.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 09:55:30 -0700 (PDT) From: Johan Jonker To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, heiko@sntech.de, peng.fan@nxp.com, jh80.chung@samsung.com, u-boot@lists.denx.de Subject: [PATCH v5 08/13] rockchip: mmc: rockchip_dw_mmc: add rk3066/rk3188 support Date: Sat, 9 Apr 2022 18:55:09 +0200 Message-Id: <20220409165514.19220-9-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220409165514.19220-1-jbx6244@gmail.com> References: <20220409165514.19220-1-jbx6244@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The Rockchip SoCs rk3066/rk3188 have MMC DT nodes with as compatible string "rockchip,rk2928-dw-mshc". Add OF_PLATDATA support to the existing driver with help of a DM_DRIVER_ALIAS. This type needs a permanent enabled fifo. The other Rockchip SoCs always have the property "u-boot,spl-fifo-mode" in the MMC DT nodes, because MMC to SRAM can't do DMA. Make this property a requirement for MMC OF_PLATDATA structures. The property "fifo-mode" must be added for all other compile modes. Signed-off-by: Johan Jonker --- Changed V5: reword remove driver_data add OF_PLATDATA u_boot_spl_fifo_mode requirement Changed V4: use boolean --- drivers/mmc/rockchip_dw_mmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index be065ec0c3..573bf16c87 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -119,7 +119,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) host->priv = dev; host->dev_index = 0; priv->fifo_depth = dtplat->fifo_depth; - priv->fifo_mode = 0; + priv->fifo_mode = dtplat->u_boot_spl_fifo_mode; priv->minmax[0] = 400000; /* 400 kHz */ priv->minmax[1] = dtplat->max_frequency; @@ -180,5 +180,6 @@ U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = { .plat_auto = sizeof(struct rockchip_mmc_plat), }; +DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk2928_dw_mshc) DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc) DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc) -- 2.20.1