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* [PATCH v2] crypto/fsl: add invalidate_dcache_range for hash output buffer
@ 2022-04-19  5:22 Gaurav Jain
  2022-04-22  8:46 ` sbabic
  0 siblings, 1 reply; 2+ messages in thread
From: Gaurav Jain @ 2022-04-19  5:22 UTC (permalink / raw)
  To: Stefano Babic, u-boot
  Cc: Fabio Estevam, Priyanka Jain, Ye Li, Horia Geanta,
	Silvano Di Ninno, Varun Sethi, Breno Lima, NXP i . MX U-Boot Team,
	Gaurav Jain, Fabio Estevam

HW accelerated hash operations are giving incorrect hash output.
so invalidate cache lines to avoid cache overwriting in DDR memory region.

caam_hash()
 -moved address alignment check in the beginning of function.
 -added invalidate_dcache_range for pout buffer before running descriptor.

Fixes: d7af2baa49 (crypto/fsl: Fix HW accelerated hash commands)
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
---
 drivers/crypto/fsl/fsl_hash.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index 2379b70c2d..a52c4ac957 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -168,18 +168,18 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
 	uint32_t *desc;
 	unsigned int size;
 
-	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
-	if (!desc) {
-		debug("Not enough memory for descriptor allocation\n");
-		return -ENOMEM;
-	}
-
 	if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) ||
 	    !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) {
 		puts("Error: Address arguments are not aligned\n");
 		return -EINVAL;
 	}
 
+	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
+	if (!desc) {
+		debug("Not enough memory for descriptor allocation\n");
+		return -ENOMEM;
+	}
+
 	size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
 	flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size);
 
@@ -190,6 +190,8 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
 
 	size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
 	flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+	size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN);
+	invalidate_dcache_range((unsigned long)pout, (unsigned long)pout + size);
 
 	ret = run_descriptor_jr(desc);
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* [PATCH v2] crypto/fsl: add invalidate_dcache_range for hash output buffer
  2022-04-19  5:22 [PATCH v2] crypto/fsl: add invalidate_dcache_range for hash output buffer Gaurav Jain
@ 2022-04-22  8:46 ` sbabic
  0 siblings, 0 replies; 2+ messages in thread
From: sbabic @ 2022-04-22  8:46 UTC (permalink / raw)
  To: Gaurav Jain, u-boot

> HW accelerated hash operations are giving incorrect hash output.
> so invalidate cache lines to avoid cache overwriting in DDR memory region.
> caam_hash()
>  -moved address alignment check in the beginning of function.
>  -added invalidate_dcache_range for pout buffer before running descriptor.
> Fixes: d7af2baa49 (crypto/fsl: Fix HW accelerated hash commands)
> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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^ permalink raw reply	[flat|nested] 2+ messages in thread

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