From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88542C433F5 for ; Mon, 25 Apr 2022 14:49:30 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 027DF833D7; Mon, 25 Apr 2022 16:49:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="FjJ49995"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 44A3F83953; Mon, 25 Apr 2022 16:49:26 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B798F8191C for ; Mon, 25 Apr 2022 16:49:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 56C61B8185C; Mon, 25 Apr 2022 14:49:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BCBB2C385A4; Mon, 25 Apr 2022 14:49:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650898161; bh=OabvQOuLemlxZZtW57oPcAdwk2eFdAVJlEhDrdmcVTY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FjJ499953ZIY2IxtZh1qz9i1Dezxyu9+jWcldS0b/OrxLQJxS+1NPDiQeuwg8JUq+ GIR99IHVDJ7lxfTjXjsh9rq/01GFLd+yiXl7siILvR3VFCDB4yxYSanQkjaAHvJ0z0 z3RErlNLZ7Qwr+QHHlGAe0ivPcfz4/fq+gCUiLvRe46lNl/NtPQ8O7CXItGo1YkfTN H2qa/ccHXLsviVba2V3lGAxFT6pi+tCulUnDfFJ9+bny4LH+OjLVRy2fNNT1bDsTlf THPkai2olOA8rHQo9ZdvVDGUNbo5YCxj6b1HiGEZDstbTynai2qcuQE3Yj4uzf4iki Z/YQP0cJvUNWA== Received: by pali.im (Postfix) id BB6324A32; Mon, 25 Apr 2022 16:49:17 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Qiang Zhao , Shengzhou Liu , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h Date: Mon, 25 Apr 2022 16:48:23 +0200 Message-Id: <20220425144823.9831-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220407101624.15850-11-pali@kernel.org> References: <20220407101624.15850-11-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Code for changing boot source is platform generic and can be used by any P1* and P2* compatible RDB board. Not only by boards which use config header file p1_p2_rdb_pc.h. So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS. This allows to use code for resetting board and rebooting to other boot source also by other boards in future. Signed-off-by: Pali Rohár --- Changes in v2: * Fix commit message * Move macros to file p1_p2_bootsrc.h * Rewrite macros even more to be more generic and use them without custom macros in p1_p2_rdb_pc.h --- include/configs/p1_p2_bootsrc.h | 55 +++++++++++++++++++++++++++++++++ include/configs/p1_p2_rdb_pc.h | 41 ++++++------------------ 2 files changed, 64 insertions(+), 32 deletions(-) create mode 100644 include/configs/p1_p2_bootsrc.h diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h new file mode 100644 index 000000000000..a274c57786f5 --- /dev/null +++ b/include/configs/p1_p2_bootsrc.h @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár + +#include + +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#endif + +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1 + +#define __VAR_CMD(var, cmd) __stringify(var=cmd\0) +#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset) + +#ifdef __SW_NOR_BANK_LO +#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_LO_CMD(var, ...) "" +#endif + +#ifdef __SW_NOR_BANK_UP +#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_UP_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NOR +#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)) +#else +#define RST_NOR_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SPI +#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)) +#else +#define RST_SPI_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SD +#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)) +#else +#define RST_SD_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NAND +#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)) +#else +#define RST_NAND_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_PCIE +#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)) +#else +#define RST_PCIE_CMD(var, ...) "" +#endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 995bd983cef1..47bd20eeeafb 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -575,31 +575,7 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#ifdef __SW_BOOT_NOR -#define __NOR_RST_CMD \ -norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SPI -#define __SPI_RST_CMD \ -spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SD -#define __SD_RST_CMD \ -sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_NAND -#define __NAND_RST_CMD \ -nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_PCIE -#define __PCIE_RST_CMD \ -pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif +#include "p1_p2_bootsrc.h" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -626,13 +602,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -__stringify(__NOR_RST_CMD)"\0" \ -__stringify(__SPI_RST_CMD)"\0" \ -__stringify(__SD_RST_CMD)"\0" \ -__stringify(__NAND_RST_CMD)"\0" \ -__stringify(__PCIE_RST_CMD)"\0" +MAP_NOR_LO_CMD(map_lowernorbank) \ +MAP_NOR_UP_CMD(map_uppernorbank) \ +RST_NOR_CMD(norboot) \ +RST_SPI_CMD(spiboot) \ +RST_SD_CMD(sdboot) \ +RST_NAND_CMD(nandboot) \ +RST_PCIE_CMD(pciboot) \ +"" #define CONFIG_USB_FAT_BOOT \ "setenv bootargs root=/dev/ram rw " \ -- 2.20.1