From: "Marek Behún" <marek.behun@nic.cz>
To: Weijie Gao <weijie.gao@mediatek.com>
Cc: Stefan Roese <sr@denx.de>, <u-boot@lists.denx.de>,
GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
Subject: Re: [PATCH v3 00/15] Add support for MediaTek MT7621 SoC
Date: Fri, 29 Apr 2022 17:13:30 +0200 [thread overview]
Message-ID: <20220429171330.3f8e3d39@thinkpad> (raw)
In-Reply-To: <055adba5a54f3d18ea310cdc7616f212bcc6c61e.camel@mediatek.com>
On Fri, 29 Apr 2022 15:59:44 +0800
Weijie Gao <weijie.gao@mediatek.com> wrote:
> On Fri, 2022-04-29 at 08:15 +0200, Stefan Roese wrote:
> > Hi Weijie
> >
> > On 4/29/22 03:23, Weijie Gao wrote:
> > > Hi Marek,
> > >
> > > Yes. MT7621 does need such a proprietary binary for DDR
> > > initialization
> > > and calibration. That's why I submit only the ram-bootable part
> > > here.
> > >
> > > I'm considering to create a preloader to load and run DDR
> > > init&calib
> > > binary and ram-bootable u-boot image. The ram-bootable u-boot image
> > > can be appended to the proloader to form the flash-bootable
> > > bootloader.
> > >
> > > The source code of preloader will be uploaded to github.
> >
> > Just to be sure: You are not implementing this preloader as an U-Boot
> > SPL loader, as this would conflict with U-Boot's GPL compatibility?
>
> Yes. Submitting the source code of this binary also violates MTK's non-
> disclosure agreement.
Isn't it possible to submit the DDR training code in binary version,
and somehow call into it from SPL?
Marek
next prev parent reply other threads:[~2022-04-29 15:13 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-28 10:37 [PATCH v3 00/15] Add support for MediaTek MT7621 SoC Weijie Gao
2022-04-28 10:37 ` [PATCH v3 01/15] mips: mtmips: add " Weijie Gao
2022-04-28 10:37 ` [PATCH v3 02/15] mips: mtmips: add two reference boards for mt7621 Weijie Gao
2022-04-29 6:20 ` Stefan Roese
2022-04-29 7:51 ` Weijie Gao
2022-04-28 10:37 ` [PATCH v3 03/15] mips: add support for noncached_alloc() Weijie Gao
2022-04-28 10:37 ` [PATCH v3 04/15] clk: mtmips: add clock driver for MediaTek MT7621 SoC Weijie Gao
2022-04-28 10:37 ` [PATCH v3 05/15] reset: mtmips: add reset controller support " Weijie Gao
2022-04-28 10:37 ` [PATCH v3 06/15] pinctrl: mtmips: add " Weijie Gao
2022-04-28 10:37 ` [PATCH v3 07/15] nand: raw: " Weijie Gao
2022-04-28 10:38 ` [PATCH v3 08/15] usb: xhci-mtk: " Weijie Gao
2022-04-28 10:38 ` [PATCH v3 09/15] phy: mtk-tphy: " Weijie Gao
2022-04-28 10:38 ` [PATCH v3 10/15] spi: " Weijie Gao
2022-04-28 10:38 ` [PATCH v3 11/15] gpio: " Weijie Gao
2022-04-28 10:38 ` [PATCH v3 12/15] watchdog: " Weijie Gao
2022-04-28 10:38 ` [PATCH v3 13/15] mmc: mediatek: " Weijie Gao
2022-04-28 10:38 ` [PATCH v3 14/15] net: " Weijie Gao
2022-04-30 17:13 ` Ramon Fried
2022-05-05 0:44 ` Weijie Gao
2022-04-28 10:38 ` [PATCH v3 15/15] MAINTAINERS: update maintainer for MediaTek MIPS platform Weijie Gao
2022-04-28 16:19 ` [PATCH v3 00/15] Add support for MediaTek MT7621 SoC Marek Behún
2022-04-29 1:23 ` Weijie Gao
2022-04-29 6:15 ` Stefan Roese
2022-04-29 7:59 ` Weijie Gao
2022-04-29 15:13 ` Marek Behún [this message]
2022-04-30 13:31 ` Weijie Gao
2022-04-30 13:48 ` Marek Behún
2022-05-01 12:52 ` Tom Rini
2022-05-05 0:57 ` Weijie Gao
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