From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66853C433F5 for ; Sun, 1 May 2022 12:24:58 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D63D383C8C; Sun, 1 May 2022 14:24:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="DtaMWVVI"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AF2D783F0E; Sun, 1 May 2022 14:24:53 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DF8EC83BBF for ; Sun, 1 May 2022 14:24:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 906DA60DDC; Sun, 1 May 2022 12:24:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D510FC385A9; Sun, 1 May 2022 12:24:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651407889; bh=2gddnlZft3Y66yjXTmSv0kz/K0R7arTtQ7OVcRAWuqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DtaMWVVIOLlbkqXnk1XUpkQgjXXCeLgXdaOf01DglSjPCS3ug7ZRxkTZ/6jQDEc7s +gXEPuA4nBNB7n2Jkjk0H79fjjtAAcIRSfQ5n5pftUf4PwjQkGSNWPKd2pt1F0HFtX Dm+4i78dWB3JfA48nb0f5xoCqwGanbwEuuVV9Rh25bvzT/vlmmYJkwcSsrEV6vL2ZO tjiqaqVnF44LkC0+n/tBkfkY2159iYUdRzmK8ec/sgi0IYpcb6Z7G0WMTaW1iY6VB8 oWVRoQmDZBEm7lDtuaYrWTxTa9BD58I16mLm8e/BQQvfY/Dsfl/GJzfBk3pVfISuIs 8+nFZPTiHazxg== Received: by pali.im (Postfix) id 4B78896D; Sun, 1 May 2022 14:24:46 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 2/3] board: freescale: p1_p2_rdb_pc: Add workaround for non-working watchdog Date: Sun, 1 May 2022 14:23:13 +0200 Message-Id: <20220501122314.32626-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220501122314.32626-1-pali@kernel.org> References: <20220501122314.32626-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean If watchdog timer was already set to non-disabled value then it means that watchdog timer was already activated, has already expired and caused CPU reset. If this happened then due to CPLD firmware bug, writing to wd_cfg register has no effect and therefore it is not possible to reactivate watchdog timer again. Also if CPU was reset via watchdog then some peripherals like i2c do not work. Watchdog and i2c start working again after CPU reset via non-watchdog method. Implement this workaround (reset CPU when it was reset by watchdog) to make watchdog usable again. Watchdog timer logic on these P1/P2 RDB boards is connected to CPLD, not to SoC itself. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 26ea8a525228..24b5ec435e4e 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -86,6 +86,7 @@ struct cpld_data { void board_cpld_init(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg); out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); out_8(&cpld_data->status_led, CPLD_STATUS_LED); @@ -102,6 +103,23 @@ void board_cpld_init(void) * is to try to clear CPLD's system reset register as early as possible. */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); + + /* + * If watchdog timer was already set to non-disabled value then it means + * that watchdog timer was already activated, has already expired and + * caused CPU reset. If this happened then due to CPLD firmware bug, + * writing to wd_cfg register has no effect and therefore it is not + * possible to reactivate watchdog timer again. Also if CPU was reset + * via watchdog then some peripherals like i2c do not work. Watchdog and + * i2c start working again after CPU reset via non-watchdog method. + * + * So in case watchdog timer register in CPLD was already enabled then + * disable it in CPLD and reset CPU which cause new boot. Watchdog timer + * is disabled few lines above, after reading CPLD previous value. + * This logic (disabling timer before reset) prevents reboot loop. + */ + if (prev_wd_cfg != CPLD_WD_CFG) + do_reset(NULL, 0, 0, NULL); } void board_gpio_init(void) -- 2.20.1