From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFAEFC433EF for ; Sun, 1 May 2022 14:26:52 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EC15583F40; Sun, 1 May 2022 16:26:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="IzXjJcNu"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E456883F1F; Sun, 1 May 2022 16:26:06 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6B2D683F1C for ; Sun, 1 May 2022 16:25:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1F26C60EDC; Sun, 1 May 2022 14:25:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2F635C385B2; Sun, 1 May 2022 14:25:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651415157; bh=cskR7EjwS4sKt1CuLgJa1oRCqtwYlRRLvSBLq7l/5FA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IzXjJcNuSyC6IyGKcxeaAjnXUwXW92ak4KEe9pJFFN32hPTAEjcvoVNpxzeP5zem+ ZdiB+7zEhfTe3GW4emYw22Y1cuW1apAKs9HTojPh9Z7Fm1HSoqpYjXm6lt2uS64DnH Ksp+F+DCUbv1SN+1/yu1fHbh81ctzY2cZUfN2pI2Q+E7q+sZ8LtJJJEMJISmltYmQM tOr5MHrZUzVQWsgJFwzLxzOpNg66LlqGybhlEWIzrc8ssd+WwVAtgn/1DTSxNd73i+ qf3XmUGiVF9RI0QYgt3MXE1Fhify8Errzjkmdn+aE73e3/vJu0EabKQI2qv2046KHg N46h2Q60ShNuQ== Received: by pali.im (Postfix) id D8DC39E6; Sun, 1 May 2022 16:25:54 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Tom Rini Cc: u-boot@lists.denx.de Subject: [PATCH 3/6] mpc85xx: Replace magic values in BR/OR PRELIM config options by proper C macros Date: Sun, 1 May 2022 16:23:54 +0200 Message-Id: <20220501142357.16778-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220501142357.16778-1-pali@kernel.org> References: <20220501142357.16778-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean This change allows to understand how are Preliminary Base and Option registers configured and later fix improper configuration. Signed-off-by: Pali Rohár --- include/configs/P2041RDB.h | 7 ++++--- include/configs/corenet_ds.h | 8 +++++--- include/configs/p1_p2_rdb_pc.h | 11 ++++++++--- 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 687b88bd2abd..c2d7c76f6063 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -118,7 +118,8 @@ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ BR_PS_16 | BR_V) #define CONFIG_SYS_FLASH_OR_PRELIM \ - ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ + (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS | OR_GPCM_TRLX | OR_GPCM_EAD \ | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) #define CONFIG_FSL_CPLD @@ -162,11 +163,11 @@ /* NAND flash config */ #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2<