[PATCH 4/6] board: freescale: p1_p2_rdb_pc: Fix size of CPLD mapping

["Pali Rohár" <pali@kernel.org>]

Per Freescale P1021RDB Combo board CPLD Specification V4.2, CPLD memory
space on all these P1/P2 RDB-PC boards, which use Lattice FPGA for CPLD
implementation, is only 128 kB long.

So decrease mapping size from 1 MB to 128 kB.

Note that E500 core, which is on P1/P2 boards does not support Book-E page
size of 128 kB. It ignores lowest bit in size definition, so macro
BOOKE_PAGESZ_128K has same effect as BOOKE_PAGESZ_64K. Therefore for TLB
entry use BOOKE_PAGESZ_256K to cover whole 128 kB of CPLD memory space.

Signed-off-by: Pali Rohár <pali@kernel.org>
---
 board/freescale/p1_p2_rdb_pc/law.c | 2 +-
 board/freescale/p1_p2_rdb_pc/tlb.c | 3 ++-
 include/configs/p1_p2_rdb_pc.h     | 6 +++---
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 5f4d713ca569..901145ded3b0 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -8,7 +8,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_VSC7385_ENET
 	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 5931ec650bd8..ca47e15067a4 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -62,9 +62,10 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 5, BOOKE_PAGESZ_1M, 1),
 #endif
 
+	/* *I*G - CPLD 256K (effective only 128K; e500 does not support BOOKE_PAGESZ_128K) */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 6, BOOKE_PAGESZ_1M, 1),
+			0, 6, BOOKE_PAGESZ_256K, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 10, BOOKE_PAGESZ_64K, 1),
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index b567eb1a03cc..69fbb4ad8fe4 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -216,7 +216,7 @@
  *   (early boot only)
  * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
  * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
- * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
+ * 0xffa0_0000 0xffa1_ffff	CPLD		128K non-cacheable	CS3
  * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
  * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
  * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
@@ -325,10 +325,10 @@
 #else
 #define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
 #endif
-/* CPLD config size: 1Mb */
+/* CPLD config size: 128 kB */
 #define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
 					BR_PS_8 | BR_V)
-#define CONFIG_CPLD_OR_PRELIM	(OR_AM_1MB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+#define CONFIG_CPLD_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 					OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
 					OR_GPCM_EHTR | OR_GPCM_EAD)
 
-- 
2.20.1