From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EAF7FC433F5 for ; Sun, 1 May 2022 14:26:21 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0FC2E83F0E; Sun, 1 May 2022 16:26:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="NDSBqNY6"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8263383DDA; Sun, 1 May 2022 16:26:05 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5EE7383DDA for ; Sun, 1 May 2022 16:25:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D805060DDC; Sun, 1 May 2022 14:25:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 236E6C385B1; Sun, 1 May 2022 14:25:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651415156; bh=uDPKnPFPp7fJ4IDkAZEKVPNGExYRlZHX0Wra/JKAqas=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NDSBqNY6dJu4kB8ToBh0GpaIiMmjSMYXnuMyMflLkV6/iF2D1+bzANZjDa9qd4GCD wfB+ekOpye+d9Fq1F/HpwybIM8n51k6CyBqyXJBraHBitplXOmw4Pvgf0FYUAB33IZ 6uwswmjWgDmG8ESfHq+1ocNwaxRXNgUumJV2fGBobY+E45yZUPD8fU4MrRwfVhAYkk ajIQMkaf+xrsXHGrq4DCiS7JRi5h+z6IjnaqKb9d9CIKCwHc7iKwA0Z/HasilYkMfN TCj6dOjPSVaWCBc5D3FGiGLT6x+iV90wyP1bifkmF+QwzzUtcHCulSZBLn8LnpoEM7 04wDWIcr3A8og== Received: by pali.im (Postfix) id D1DB5942; Sun, 1 May 2022 16:25:55 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Tom Rini Cc: u-boot@lists.denx.de Subject: [PATCH 4/6] board: freescale: p1_p2_rdb_pc: Fix size of CPLD mapping Date: Sun, 1 May 2022 16:23:55 +0200 Message-Id: <20220501142357.16778-5-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220501142357.16778-1-pali@kernel.org> References: <20220501142357.16778-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Per Freescale P1021RDB Combo board CPLD Specification V4.2, CPLD memory space on all these P1/P2 RDB-PC boards, which use Lattice FPGA for CPLD implementation, is only 128 kB long. So decrease mapping size from 1 MB to 128 kB. Note that E500 core, which is on P1/P2 boards does not support Book-E page size of 128 kB. It ignores lowest bit in size definition, so macro BOOKE_PAGESZ_128K has same effect as BOOKE_PAGESZ_64K. Therefore for TLB entry use BOOKE_PAGESZ_256K to cover whole 128 kB of CPLD memory space. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/law.c | 2 +- board/freescale/p1_p2_rdb_pc/tlb.c | 3 ++- include/configs/p1_p2_rdb_pc.h | 6 +++--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 5f4d713ca569..901145ded3b0 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -8,7 +8,7 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 5931ec650bd8..ca47e15067a4 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -62,9 +62,10 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 5, BOOKE_PAGESZ_1M, 1), #endif + /* *I*G - CPLD 256K (effective only 128K; e500 does not support BOOKE_PAGESZ_128K) */ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_1M, 1), + 0, 6, BOOKE_PAGESZ_256K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index b567eb1a03cc..69fbb4ad8fe4 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -216,7 +216,7 @@ * (early boot only) * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 - * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 + * 0xffa0_0000 0xffa1_ffff CPLD 128K non-cacheable CS3 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable @@ -325,10 +325,10 @@ #else #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE #endif -/* CPLD config size: 1Mb */ +/* CPLD config size: 128 kB */ #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ BR_PS_8 | BR_V) -#define CONFIG_CPLD_OR_PRELIM (OR_AM_1MB | OR_GPCM_CSNT | OR_GPCM_XACS | \ +#define CONFIG_CPLD_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ OR_GPCM_SCY_15 | OR_GPCM_TRLX | \ OR_GPCM_EHTR | OR_GPCM_EAD) -- 2.20.1