From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2DD58C433EF for ; Sun, 1 May 2022 14:26:42 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3356083F2D; Sun, 1 May 2022 16:26:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="uoTpDDDa"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3268F83F05; Sun, 1 May 2022 16:26:06 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EC49783F13 for ; Sun, 1 May 2022 16:25:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 808A4B80CE1; Sun, 1 May 2022 14:25:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 16B5EC385B1; Sun, 1 May 2022 14:25:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651415157; bh=IrwRRtaOh7q/ZZVXwABPj1pLYC35p/+HVHe+MJOXdgQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uoTpDDDaWB2mNZMC+JEehsrPsRLMJvQpvAoM0CfsMg3bJwDUROl7sOudDXc0x/0ww 8ZxZlQkmfBDmvJd1QZnC65UzBvbFuxwsnN97tXatQ6GOyN+c7osAsJc+ZnplHrdzr3 3/UcjPPyE8UvqCe7+M1dEcltlL7j0BoLxRmYP1Of01qpNd43P08wl6ixzxMP5dAqdT 5dTSyUhHqx+9LBpHy4mEyrpC7xsc9T7bQcnZJW9VvyB9/7KsmqzwCrY/yCc4JPg+GG 2ckwdf0HyOawt4VGExQQXjDwLc1znrbdI6zLULBxHY3aEBF1TNh/NQpdvwPUDJ1DDY jNOqYdtZ4FCYg== Received: by pali.im (Postfix) id C5B71942; Sun, 1 May 2022 16:25:56 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Tom Rini Cc: u-boot@lists.denx.de Subject: [PATCH 5/6] board: freescale: p1_p2_rdb_pc: Fix size of FLASH NOR mapping Date: Sun, 1 May 2022 16:23:56 +0200 Message-Id: <20220501142357.16778-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220501142357.16778-1-pali@kernel.org> References: <20220501142357.16778-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean FLASH NOR on P1020RDB-PD has size of 64 MB. On all other P1/P2 RDB boards it has only size of 16 MB. So fix this size in TLB, LAW and LBC OR registers. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/law.c | 4 ++++ board/freescale/p1_p2_rdb_pc/tlb.c | 6 ++++++ include/configs/p1_p2_rdb_pc.h | 7 +++++++ 3 files changed, 17 insertions(+) diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 901145ded3b0..80adf21a1183 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -13,7 +13,11 @@ struct law_entry law_table[] = { #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#ifdef CONFIG_TARGET_P1020RDB_PD SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#else + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), +#endif #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), #endif diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index ca47e15067a4..5bbeae302ad0 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -39,9 +39,15 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ +#ifdef CONFIG_TARGET_P1020RDB_PD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1), +#else + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_16M, 1), +#endif #ifdef CONFIG_PCI /* *I*G* - PCI memory 1.5G */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 69fbb4ad8fe4..cf84f4045538 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -243,10 +243,17 @@ #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_FLASH_OR_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \ OR_GPCM_SCY_15 | OR_GPCM_TRLX | \ OR_GPCM_EHTR | OR_GPCM_EAD) +#else +#define CONFIG_FLASH_OR_PRELIM (OR_AM_16MB | OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \ + OR_GPCM_SCY_15 | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) +#endif #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST -- 2.20.1