Re: [PATCH 06/12] ARM: dts: sun9i: Sync from Linux v5.18-rc1

Andre Przywara
2022-05-20T15:35:40Z

On Wed, 27 Apr 2022 15:31:25 -0500
Samuel Holland <samuel@sholland.org> wrote:

Hi,

> Copy the devicetree source for the A80 SoC and all existing boards
> verbatim from the Linux v5.18-rc1 tag.
>
> This update should not impact any existing U-Boot functionality.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Compared against the respective kernel tree's files, they are identical.

Change-wise the "dumb-vga-dac" compatible is dropped from the Cubieboard,
but the others are supported since v4.12, so that should not matter.
Also the new IR compatible string requires a v5.4 kernel, but since that's
not really a critical component, this is probably fine as well.

So with that:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Thanks!
Andre

> ---
>
> arch/arm/dts/sun9i-a80-cubieboard4.dts | 67 ++++++---
> arch/arm/dts/sun9i-a80-optimus.dts | 50 ++++++-
> arch/arm/dts/sun9i-a80.dtsi | 195 +++++++++++++++----------
> 3 files changed, 212 insertions(+), 100 deletions(-)
>
> diff --git a/arch/arm/dts/sun9i-a80-cubieboard4.dts b/arch/arm/dts/sun9i-a80-cubieboard4.dts
> index 85da85faf8..c8ca8cb7f5 100644
> --- a/arch/arm/dts/sun9i-a80-cubieboard4.dts
> +++ b/arch/arm/dts/sun9i-a80-cubieboard4.dts
> @@ -63,12 +63,12 @@
> leds {
> compatible = "gpio-leds";
>
> - green {
> + led-0 {
> label = "cubieboard4:green:usr";
> gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */
> };
>
> - red {
> + led-1 {
> label = "cubieboard4:red:usr";
> gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
> };
> @@ -87,33 +87,25 @@
> };
>
> vga-dac {
> - compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac";
> + compatible = "corpro,gm7123", "adi,adv7123";
> vdd-supply = <&reg_dcdc1>;
> - #address-cells = <1>;
> - #size-cells = <0>;
>
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - vga_dac_in: endpoint@0 {
> - reg = <0>;
> + vga_dac_in: endpoint {
> remote-endpoint = <&tcon0_out_vga>;
> };
> };
>
> port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - vga_dac_out: endpoint@0 {
> - reg = <0>;
> + vga_dac_out: endpoint {
> remote-endpoint = <&vga_con_in>;
> };
> };
> @@ -133,12 +125,27 @@
> status = "okay";
> };
>
> +&gmac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac_rgmii_pins>;
> + phy-handle = <&phy1>;
> + phy-mode = "rgmii-id";
> + phy-supply = <&reg_cldo1>;
> + status = "okay";
> +};
> +
> &i2c3 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c3_pins>;
> status = "okay";
> };
>
> +&mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins>;
> @@ -183,10 +190,26 @@
> clocks = <&ac100_rtc 0>;
> };
>
> +&pio {
> + vcc-pa-supply = <&reg_ldo_io1>;
> + vcc-pb-supply = <&reg_aldo2>;
> + vcc-pc-supply = <&reg_dcdc1>;
> + vcc-pd-supply = <&reg_dc1sw>;
> + vcc-pe-supply = <&reg_eldo2>;
> + vcc-pf-supply = <&reg_dcdc1>;
> + vcc-pg-supply = <&reg_ldo_io0>;
> + vcc-ph-supply = <&reg_dcdc1>;
> +};
> +
> &r_ir {
> status = "okay";
> };
>
> +&r_pio {
> + vcc-pl-supply = <&reg_dldo2>;
> + vcc-pm-supply = <&reg_eldo3>;
> +};
> +
> &r_rsb {
> status = "okay";
>
> @@ -217,6 +240,10 @@
> /* unused */
> };
>
> + reg_dc1sw: dc1sw {
> + regulator-name = "vcc-pd";
> + };
> +
> reg_dc5ldo: dc5ldo {
> regulator-always-on;
> regulator-min-microvolt = <800000>;
> @@ -271,7 +298,6 @@
> };
>
> reg_dldo2: dldo2 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pl";
> @@ -290,14 +316,12 @@
> };
>
> reg_eldo3: eldo3 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pm-codec-io1";
> };
>
> reg_ldo_io0: ldo_io0 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pg";
> @@ -385,6 +409,14 @@
> */
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> + /*
> + * The PHY requires 20ms after all voltages
> + * are applied until core logic is ready and
> + * 30ms after the reset pin is de-asserted.
> + * Set a 100ms delay to account for PMIC
> + * ramp time and board traces.
> + */
> + regulator-enable-ramp-delay = <100000>;
> regulator-name = "vcc-gmac-phy";
> };
>
> @@ -464,8 +496,7 @@
> };
>
> &tcon0_out {
> - tcon0_out_vga: endpoint@0 {
> - reg = <0>;
> + tcon0_out_vga: endpoint {
> remote-endpoint = <&vga_dac_in>;
> };
> };
> diff --git a/arch/arm/dts/sun9i-a80-optimus.dts b/arch/arm/dts/sun9i-a80-optimus.dts
> index 58a199b0e4..5c3580d712 100644
> --- a/arch/arm/dts/sun9i-a80-optimus.dts
> +++ b/arch/arm/dts/sun9i-a80-optimus.dts
> @@ -82,7 +82,7 @@
>
> reg_usb1_vbus: usb1-vbus {
> compatible = "regulator-fixed";
> - pinctrl-names = "default";
> + regulator-name = "usb1-vbus";
> regulator-min-microvolt = <5000000>;
> regulator-max-microvolt = <5000000>;
> enable-active-high;
> @@ -91,7 +91,7 @@
>
> reg_usb3_vbus: usb3-vbus {
> compatible = "regulator-fixed";
> - pinctrl-names = "default";
> + regulator-name = "usb3-vbus";
> regulator-min-microvolt = <5000000>;
> regulator-max-microvolt = <5000000>;
> enable-active-high;
> @@ -120,6 +120,21 @@
> status = "okay";
> };
>
> +&gmac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac_rgmii_pins>;
> + phy-handle = <&phy1>;
> + phy-mode = "rgmii-id";
> + phy-supply = <&reg_cldo1>;
> + status = "okay";
> +};
> +
> +&mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins>;
> @@ -172,10 +187,26 @@
> clocks = <&ac100_rtc 0>;
> };
>
> +&pio {
> + vcc-pa-supply = <&reg_ldo_io1>;
> + vcc-pb-supply = <&reg_aldo2>;
> + vcc-pc-supply = <&reg_dcdc1>;
> + vcc-pd-supply = <&reg_dcdc1>;
> + vcc-pe-supply = <&reg_eldo2>;
> + vcc-pf-supply = <&reg_dcdc1>;
> + vcc-pg-supply = <&reg_ldo_io0>;
> + vcc-ph-supply = <&reg_dcdc1>;
> +};
> +
> &r_ir {
> status = "okay";
> };
>
> +&r_pio {
> + vcc-pl-supply = <&reg_dldo2>;
> + vcc-pm-supply = <&reg_eldo3>;
> +};
> +
> &r_rsb {
> status = "okay";
>
> @@ -213,6 +244,10 @@
> regulator-name = "vdd-cpus-09-usbh";
> };
>
> + dc1sw {
> + /* unused */
> + };
> +
> reg_dcdc1: dcdc1 {
> regulator-always-on;
> regulator-min-microvolt = <3000000>;
> @@ -260,7 +295,6 @@
> };
>
> reg_dldo2: dldo2 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pl";
> @@ -279,14 +313,12 @@
> };
>
> reg_eldo3: eldo3 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pm-codec-io1";
> };
>
> reg_ldo_io0: ldo_io0 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pg";
> @@ -374,6 +406,14 @@
> */
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> + /*
> + * The PHY requires 20ms after all voltages
> + * are applied until core logic is ready and
> + * 30ms after the reset pin is de-asserted.
> + * Set a 100ms delay to account for PMIC
> + * ramp time and board traces.
> + */
> + regulator-enable-ramp-delay = <100000>;
> regulator-name = "vcc-gmac-phy";
> };
>
> diff --git a/arch/arm/dts/sun9i-a80.dtsi b/arch/arm/dts/sun9i-a80.dtsi
> index 25591d6883..ce4fa6706d 100644
> --- a/arch/arm/dts/sun9i-a80.dtsi
> +++ b/arch/arm/dts/sun9i-a80.dtsi
> @@ -56,6 +56,10 @@
> #size-cells = <2>;
> interrupt-parent = <&gic>;
>
> + aliases {
> + ethernet0 = &gmac;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -183,6 +187,37 @@
> clock-output-names = "osc32k";
> };
>
> + /*
> + * The following two are dummy clocks, placeholders
> + * used in the gmac_tx clock. The gmac driver will
> + * choose one parent depending on the PHY interface
> + * mode, using clk_set_rate auto-reparenting.
> + *
> + * The actual TX clock rate is not controlled by the
> + * gmac_tx clock.
> + */
> + mii_phy_tx_clk: mii_phy_tx_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <25000000>;
> + clock-output-names = "mii_phy_tx";
> + };
> +
> + gmac_int_tx_clk: gmac_int_tx_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + clock-output-names = "gmac_int_tx";
> + };
> +
> + gmac_tx_clk: clk@800030 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun7i-a20-gmac-clk";
> + reg = <0x00800030 0x4>;
> + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
> + clock-output-names = "gmac_tx";
> + };
> +
> cpus_clk: clk@8001410 {
> compatible = "allwinner,sun9i-a80-cpus-clk";
> reg = <0x08001410 0x4>;
> @@ -254,7 +289,7 @@
> status = "disabled";
> };
>
> - soc {
> + soc@20000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -283,6 +318,27 @@
> };
> };
>
> + gmac: ethernet@830000 {
> + compatible = "allwinner,sun7i-a20-gmac";
> + reg = <0x00830000 0x1054>;
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
> + clock-names = "stmmaceth", "allwinner_gmac_tx";
> + resets = <&ccu RST_BUS_GMAC>;
> + reset-names = "stmmaceth";
> + snps,pbl = <2>;
> + snps,fixed-burst;
> + snps,force_sf_dma_mode;
> + status = "disabled";
> +
> + mdio: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> ehci0: usb@a00000 {
> compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
> reg = <0x00a00000 0x100>;
> @@ -331,16 +387,16 @@
> usbphy2: phy@a01800 {
> compatible = "allwinner,sun9i-a80-usb-phy";
> reg = <0x00a01800 0x4>;
> - clocks = <&usb_clocks CLK_USB1_HSIC>,
> + clocks = <&usb_clocks CLK_USB1_PHY>,
> <&usb_clocks CLK_USB_HSIC>,
> - <&usb_clocks CLK_USB1_PHY>;
> - clock-names = "hsic_480M",
> + <&usb_clocks CLK_USB1_HSIC>;
> + clock-names = "phy",
> "hsic_12M",
> - "phy";
> - resets = <&usb_clocks RST_USB1_HSIC>,
> - <&usb_clocks RST_USB1_PHY>;
> - reset-names = "hsic",
> - "phy";
> + "hsic_480M";
> + resets = <&usb_clocks RST_USB1_PHY>,
> + <&usb_clocks RST_USB1_HSIC>;
> + reset-names = "phy",
> + "hsic";
> status = "disabled";
> #phy-cells = <0>;
> /* usb1 is always used with HSIC */
> @@ -373,16 +429,16 @@
> usbphy3: phy@a02800 {
> compatible = "allwinner,sun9i-a80-usb-phy";
> reg = <0x00a02800 0x4>;
> - clocks = <&usb_clocks CLK_USB2_HSIC>,
> + clocks = <&usb_clocks CLK_USB2_PHY>,
> <&usb_clocks CLK_USB_HSIC>,
> - <&usb_clocks CLK_USB2_PHY>;
> - clock-names = "hsic_480M",
> + <&usb_clocks CLK_USB2_HSIC>;
> + clock-names = "phy",
> "hsic_12M",
> - "phy";
> - resets = <&usb_clocks RST_USB2_HSIC>,
> - <&usb_clocks RST_USB2_PHY>;
> - reset-names = "hsic",
> - "phy";
> + "hsic_480M";
> + resets = <&usb_clocks RST_USB2_PHY>,
> + <&usb_clocks RST_USB2_HSIC>;
> + reset-names = "phy",
> + "hsic";
> status = "disabled";
> #phy-cells = <0>;
> };
> @@ -401,6 +457,15 @@
> reg = <0x01700000 0x100>;
> };
>
> + crypto: crypto@1c02000 {
> + compatible = "allwinner,sun9i-a80-crypto";
> + reg = <0x01c02000 0x1000>;
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&ccu RST_BUS_SS>;
> + clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
> + clock-names = "bus", "mod";
> + };
> +
> mmc0: mmc@1c0f000 {
> compatible = "allwinner,sun9i-a80-mmc";
> reg = <0x01c0f000 0x1000>;
> @@ -465,9 +530,7 @@
> compatible = "allwinner,sun9i-a80-mmc-config-clk";
> reg = <0x01c13000 0x10>;
> clocks = <&ccu CLK_BUS_MMC>;
> - clock-names = "ahb";
> resets = <&ccu RST_BUS_MMC>;
> - reset-names = "ahb";
> #clock-cells = <1>;
> #reset-cells = <1>;
> clock-output-names = "mmc0_config", "mmc1_config",
> @@ -475,7 +538,7 @@
> };
>
> gic: interrupt-controller@1c41000 {
> - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + compatible = "arm,gic-400";
> reg = <0x01c41000 0x1000>,
> <0x01c42000 0x2000>,
> <0x01c44000 0x2000>,
> @@ -544,12 +607,9 @@
> #size-cells = <0>;
>
> fe0_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - fe0_out_deu0: endpoint@0 {
> - reg = <0>;
> + fe0_out_deu0: endpoint {
> remote-endpoint = <&deu0_in_fe0>;
> };
> };
> @@ -571,12 +631,9 @@
> #size-cells = <0>;
>
> fe1_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - fe1_out_deu1: endpoint@0 {
> - reg = <0>;
> + fe1_out_deu1: endpoint {
> remote-endpoint = <&deu1_in_fe1>;
> };
> };
> @@ -614,12 +671,9 @@
> };
>
> be0_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - be0_out_drc0: endpoint@0 {
> - reg = <0>;
> + be0_out_drc0: endpoint {
> remote-endpoint = <&drc0_in_be0>;
> };
> };
> @@ -657,12 +711,9 @@
> };
>
> be1_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - be1_out_drc1: endpoint@0 {
> - reg = <0>;
> + be1_out_drc1: endpoint {
> remote-endpoint = <&drc1_in_be1>;
> };
> };
> @@ -686,12 +737,9 @@
> #size-cells = <0>;
>
> deu0_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - deu0_in_fe0: endpoint@0 {
> - reg = <0>;
> + deu0_in_fe0: endpoint {
> remote-endpoint = <&fe0_out_deu0>;
> };
> };
> @@ -731,12 +779,9 @@
> #size-cells = <0>;
>
> deu1_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - deu1_in_fe1: endpoint@0 {
> - reg = <0>;
> + deu1_in_fe1: endpoint {
> remote-endpoint = <&fe1_out_deu1>;
> };
> };
> @@ -776,23 +821,17 @@
> #size-cells = <0>;
>
> drc0_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - drc0_in_be0: endpoint@0 {
> - reg = <0>;
> + drc0_in_be0: endpoint {
> remote-endpoint = <&be0_out_drc0>;
> };
> };
>
> drc0_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - drc0_out_tcon0: endpoint@0 {
> - reg = <0>;
> + drc0_out_tcon0: endpoint {
> remote-endpoint = <&tcon0_in_drc0>;
> };
> };
> @@ -816,23 +855,17 @@
> #size-cells = <0>;
>
> drc1_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - drc1_in_be1: endpoint@0 {
> - reg = <0>;
> + drc1_in_be1: endpoint {
> remote-endpoint = <&be1_out_drc1>;
> };
> };
>
> drc1_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - drc1_out_tcon1: endpoint@0 {
> - reg = <0>;
> + drc1_out_tcon1: endpoint {
> remote-endpoint = <&tcon1_in_drc1>;
> };
> };
> @@ -845,28 +878,28 @@
> interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
> clock-names = "ahb", "tcon-ch0";
> - resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
> - reset-names = "lcd", "edp";
> + resets = <&ccu RST_BUS_LCD0>,
> + <&ccu RST_BUS_EDP>,
> + <&ccu RST_BUS_LVDS>;
> + reset-names = "lcd",
> + "edp",
> + "lvds";
> clock-output-names = "tcon0-pixel-clock";
> + #clock-cells = <0>;
>
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> tcon0_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - tcon0_in_drc0: endpoint@0 {
> - reg = <0>;
> + tcon0_in_drc0: endpoint {
> remote-endpoint = <&drc0_out_tcon0>;
> };
> };
>
> tcon0_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
> };
> };
> @@ -886,19 +919,14 @@
> #size-cells = <0>;
>
> tcon1_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - tcon1_in_drc1: endpoint@0 {
> - reg = <0>;
> + tcon1_in_drc1: endpoint {
> remote-endpoint = <&drc1_out_tcon1>;
> };
> };
>
> tcon1_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
> };
> };
> @@ -930,6 +958,7 @@
> compatible = "allwinner,sun6i-a31-wdt";
> reg = <0x06000ca0 0x20>;
> interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> };
>
> pio: pinctrl@6000800 {
> @@ -945,9 +974,20 @@
> gpio-controller;
> interrupt-controller;
> #interrupt-cells = <3>;
> - #size-cells = <0>;
> #gpio-cells = <3>;
>
> + gmac_rgmii_pins: gmac-rgmii-pins {
> + pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
> + "PA7", "PA8", "PA9", "PA10", "PA12",
> + "PA13", "PA15", "PA16", "PA17";
> + function = "gmac";
> + /*
> + * data lines in RGMII mode use DDR mode
> + * and need a higher signal drive strength
> + */
> + drive-strength = <40>;
> + };
> +
> i2c3_pins: i2c3-pins {
> pins = "PG10", "PG11";
> function = "i2c3";
> @@ -1126,6 +1166,7 @@
> compatible = "allwinner,sun6i-a31-wdt";
> reg = <0x08001000 0x20>;
> interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> };
>
> prcm@8001400 {
> @@ -1148,7 +1189,7 @@
> };
>
> r_ir: ir@8002000 {
> - compatible = "allwinner,sun5i-a13-ir";
> + compatible = "allwinner,sun6i-a31-ir";
> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&r_ir_pins>;
> @@ -1196,7 +1237,7 @@
> };
> };
>
> - r_rsb: i2c@8003400 {
> + r_rsb: rsb@8003400 {
> compatible = "allwinner,sun8i-a23-rsb";
> reg = <0x08003400 0x400>;
> interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;