Re: [PATCH 08/12] ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1

Andre Przywara
2022-05-22T23:35:37Z

On Wed, 27 Apr 2022 15:31:27 -0500
Samuel Holland <samuel@sholland.org> wrote:

> Copy the devicetree source for the H2+/H3/H5 SoCs and all existing
> boards from the Linux v5.18-rc1 tag.
>
> To maintain ABI compatibility with existing LTS kernels, one change
> moving some IP blocks to the r_intc interrupt controller is excluded.
> This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
>
> This commit also adds the following new board devicetree:
> - sun8i-h3-nanopi-r1.dts
>
> This update should not impact any existing U-Boot functionality.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Looks good, the files are the same as in the kernel tree, minus the
r_intc change.
There seems to be a compatible name change for the H5 for the
mbus device, but that should only affect the interlace device, and I
actually don't see a driver using the old compatible name in the tree
at all. So:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 9 +-
> arch/arm/dts/sun50i-h5.dtsi | 6 +-
> .../dts/sun8i-h2-plus-bananapi-m2-zero.dts | 28 ++-
> arch/arm/dts/sun8i-h3-beelink-x2.dts | 27 ++-
> arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 28 +++
> arch/arm/dts/sun8i-h3-nanopi-r1.dts | 169 ++++++++++++++++++
> arch/arm/dts/sun8i-h3-nanopi.dtsi | 1 +
> arch/arm/dts/sun8i-h3-orangepi-2.dts | 3 +-
> arch/arm/dts/sun8i-h3-orangepi-pc.dts | 3 +-
> arch/arm/dts/sun8i-h3.dtsi | 10 +-
> arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 18 +-
> arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 4 +-
> arch/arm/dts/sunxi-h3-h5.dtsi | 42 ++++-
> arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi | 13 ++
> arch/arm/dts/sunxi-libretech-all-h3-it.dtsi | 2 +-
> 17 files changed, 342 insertions(+), 24 deletions(-)
> create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 6433f63455..bbd69d3a67 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -655,6 +655,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
> sun8i-h3-nanopi-m1-plus.dtb \
> sun8i-h3-nanopi-neo.dtb \
> sun8i-h3-nanopi-neo-air.dtb \
> + sun8i-h3-nanopi-r1.dtb \
> sun8i-h3-orangepi-2.dtb \
> sun8i-h3-orangepi-lite.dtb \
> sun8i-h3-orangepi-one.dtb \
> diff --git a/arch/arm/dts/sun50i-h5-cpu-opp.dtsi b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
> index b265720195..1afad8b437 100644
> --- a/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
> +++ b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
> @@ -2,7 +2,7 @@
> // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
>
> / {
> - cpu_opp_table: cpu-opp-table {
> + cpu_opp_table: opp-table-cpu {
> compatible = "operating-points-v2";
> opp-shared;
>
> diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
> index 55bcdf8d1a..55b369534a 100644
> --- a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
> +++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
> @@ -142,9 +142,16 @@
> status = "okay";
>
> eeprom@51 {
> - compatible = "microchip,24c02";
> + compatible = "microchip,24c02", "atmel,24c02";
> reg = <0x51>;
> pagesize = <16>;
> + read-only;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + eth_mac1: mac-address@fa {
> + reg = <0xfa 0x06>;
> + };
> };
> };
>
> diff --git a/arch/arm/dts/sun50i-h5.dtsi b/arch/arm/dts/sun50i-h5.dtsi
> index ab860e20d0..9b3462b13c 100644
> --- a/arch/arm/dts/sun50i-h5.dtsi
> +++ b/arch/arm/dts/sun50i-h5.dtsi
> @@ -217,7 +217,7 @@
> };
> };
>
> - gpu_thermal {
> + gpu-thermal {
> polling-delay-passive = <0>;
> polling-delay = <0>;
> thermal-sensors = <&ths 1>;
> @@ -233,6 +233,10 @@
> compatible = "allwinner,sun50i-h5-de2-clk";
> };
>
> +&mbus {
> + compatible = "allwinner,sun50i-h5-mbus";
> +};
> +
> &mmc0 {
> compatible = "allwinner,sun50i-h5-mmc",
> "allwinner,sun50i-a64-mmc";
> diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
> index f3f7a2c912..d5c7b7984d 100644
> --- a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
> +++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
> @@ -26,6 +26,17 @@
> stdout-path = "serial0:115200n8";
> };
>
> + connector {
> + compatible = "hdmi-connector";
> + type = "c";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> leds {
> compatible = "gpio-leds";
>
> @@ -41,8 +52,9 @@
>
> sw4 {
> label = "power";
> - linux,code = <BTN_0>;
> + linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
>
> @@ -103,10 +115,24 @@
> cpu-supply = <&reg_vdd_cpux>;
> };
>
> +&de {
> + status = "okay";
> +};
> +
> &ehci0 {
> status = "okay";
> };
>
> +&hdmi {
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <&reg_vcc3v3>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts
> index 62b5280ec0..cd9f655e4f 100644
> --- a/arch/arm/dts/sun8i-h3-beelink-x2.dts
> +++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts
> @@ -57,6 +57,12 @@
> ethernet1 = &sdiowifi;
> };
>
> + cec-gpio {
> + compatible = "cec-gpio";
> + cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */
> + hdmi-phandle = <&hdmi>;
> + };
> +
> chosen {
> stdout-path = "serial0:115200n8";
> };
> @@ -87,11 +93,15 @@
> };
> };
>
> - wifi_pwrseq: wifi_pwrseq {
> - compatible = "mmc-pwrseq-simple";
> - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
> - clocks = <&rtc 1>;
> - clock-names = "ext_clock";
> + r-gpio-keys {
> + compatible = "gpio-keys";
> +
> + power {
> + label = "power";
> + linux,code = <KEY_POWER>;
> + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> + };
> };
>
> sound_spdif {
> @@ -111,6 +121,13 @@
> #sound-dai-cells = <0>;
> compatible = "linux,spdif-dit";
> };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
> + clocks = <&rtc 1>;
> + clock-names = "ext_clock";
> + };
> };
>
> &de {
> diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
> index be49eabbff..cd3df12b65 100644
> --- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
> +++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
> @@ -103,12 +103,40 @@
> };
> };
>
> +&mmc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc2_8bit_pins>;
> + vmmc-supply = <&reg_vcc3v3>;
> + vqmmc-supply = <&reg_vcc3v3>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_pa_pins>;
> status = "okay";
> };
>
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + clocks = <&rtc 1>;
> + clock-names = "lpo";
> + vbat-supply = <&reg_vcc3v3>;
> + vddio-supply = <&reg_vcc3v3>;
> + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
> + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
> + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
> + };
> +};
> +
> &usbphy {
> /* USB VBUS is always on */
> status = "okay";
> diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
> new file mode 100644
> index 0000000000..26e2e6172e
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>
> + * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
> + * Copyright (C) 2020 Yu-Tung Chang <mtwget@gmail.com>
> +*/
> +
> +#include "sun8i-h3-nanopi.dtsi"
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> + model = "FriendlyARM NanoPi R1";
> + compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3";
> +
> + aliases {
> + serial1 = &uart1;
> + ethernet0 = &emac;
> + ethernet1 = &wifi;
> + };
> +
> + reg_gmac_3v3: gmac-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "gmac-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + startup-delay-us = <100000>;
> + enable-active-high;
> + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
> + };
> +
> + reg_vdd_cpux: gpio-regulator {
> + compatible = "regulator-gpio";
> + regulator-name = "vdd-cpux";
> + regulator-type = "voltage";
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-ramp-delay = <50>;
> + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
> + gpios-states = <0x1>;
> + states = <1100000 0x0>,
> + <1300000 0x1>;
> + };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
> + clocks = <&rtc 1>;
> + clock-names = "ext_clock";
> + };
> +
> + leds {
> + led-2 {
> + function = LED_FUNCTION_WAN;
> + color = <LED_COLOR_ID_GREEN>;
> + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
> + };
> +
> + led-3 {
> + function = LED_FUNCTION_LAN;
> + color = <LED_COLOR_ID_GREEN>;
> + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; /* PA9 */
> + };
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&reg_vdd_cpux>;
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&ehci2 {
> + status = "okay";
> +};
> +
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <&reg_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@7 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + };
> +};
> +
> +&mmc1 {
> + vmmc-supply = <&reg_vcc3v3>;
> + vqmmc-supply = <&reg_vcc3v3>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +
> + wifi: wifi@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + interrupt-parent = <&pio>;
> + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
> + interrupt-names = "host-wake";
> + };
> +};
> +
> +&mmc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc2_8bit_pins>;
> + vmmc-supply = <&reg_vcc3v3>;
> + vqmmc-supply = <&reg_vcc3v3>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&ohci2 {
> + status = "okay";
> +};
> +
> +&reg_usb0_vbus {
> + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + clocks = <&rtc 1>;
> + clock-names = "lpo";
> + vbat-supply = <&reg_vcc3v3>;
> + vddio-supply = <&reg_vcc3v3>;
> + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
> + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
> + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
> + };
> +};
> +
> +&usb_otg {
> + status = "okay";
> + dr_mode = "otg";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
> + usb0_vbus-supply = <&reg_usb0_vbus>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun8i-h3-nanopi.dtsi b/arch/arm/dts/sun8i-h3-nanopi.dtsi
> index c7c3e7d8b3..fc45d5aaa6 100644
> --- a/arch/arm/dts/sun8i-h3-nanopi.dtsi
> +++ b/arch/arm/dts/sun8i-h3-nanopi.dtsi
> @@ -81,6 +81,7 @@
> label = "k1";
> linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
> };
> diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts
> index 597c425d08..9daffd90c1 100644
> --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts
> +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts
> @@ -99,8 +99,9 @@
>
> sw4 {
> label = "sw4";
> - linux,code = <BTN_0>;
> + linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
>
> diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
> index 5aff8ecc66..90f75fa85e 100644
> --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts
> +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
> @@ -91,8 +91,9 @@
>
> sw4 {
> label = "sw4";
> - linux,code = <BTN_0>;
> + linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
> };
> diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
> index 4e89701df9..eac2349a23 100644
> --- a/arch/arm/dts/sun8i-h3.dtsi
> +++ b/arch/arm/dts/sun8i-h3.dtsi
> @@ -44,7 +44,7 @@
> #include <dt-bindings/thermal/thermal.h>
>
> / {
> - cpu0_opp_table: opp_table0 {
> + cpu0_opp_table: opp-table-cpu {
> compatible = "operating-points-v2";
> opp-shared;
>
> @@ -112,7 +112,7 @@
> };
> };
>
> - gpu_opp_table: gpu-opp-table {
> + gpu_opp_table: opp-table-gpu {
> compatible = "operating-points-v2";
>
> opp-120000000 {
> @@ -245,7 +245,7 @@
> cpu_thermal: cpu-thermal {
> polling-delay-passive = <0>;
> polling-delay = <0>;
> - thermal-sensors = <&ths 0>;
> + thermal-sensors = <&ths>;
>
> trips {
> cpu_hot_trip: cpu-hot {
> @@ -282,6 +282,10 @@
> compatible = "allwinner,sun8i-h3-de2-clk";
> };
>
> +&mbus {
> + compatible = "allwinner,sun8i-h3-mbus";
> +};
> +
> &mmc0 {
> compatible = "allwinner,sun7i-a20-mmc";
> clocks = <&ccu CLK_BUS_MMC0>,
> diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
> index 22466afd38..235994a4a2 100644
> --- a/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
> +++ b/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
> @@ -16,15 +16,27 @@
> regulator-type = "voltage";
> regulator-boot-on;
> regulator-always-on;
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1300000>;
> + regulator-min-microvolt = <1108475>;
> + regulator-max-microvolt = <1308475>;
> regulator-ramp-delay = <50>; /* 4ms */
> gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
> gpios-states = <0x1>;
> - states = <1100000 0>, <1300000 1>;
> + states = <1108475 0>, <1308475 1>;
> };
> };
>
> &cpu0 {
> cpu-supply = <&reg_vdd_cpux>;
> };
> +
> +&cpu1 {
> + cpu-supply = <&reg_vdd_cpux>;
> +};
> +
> +&cpu2 {
> + cpu-supply = <&reg_vdd_cpux>;
> +};
> +
> +&cpu3 {
> + cpu-supply = <&reg_vdd_cpux>;
> +};
> diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
> index 8e5cb3b3fd..d03f5853ef 100644
> --- a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
> +++ b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
> @@ -82,8 +82,9 @@
>
> sw4 {
> label = "power";
> - linux,code = <BTN_0>;
> + linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
>
> @@ -219,6 +220,7 @@
>
> bluetooth {
> compatible = "brcm,bcm43438-bt";
> + max-speed = <1500000>;
> clocks = <&rtc 1>;
> clock-names = "lpo";
> vbat-supply = <&reg_vcc3v3>;
> diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi
> index 9be13378d4..6cea57e07f 100644
> --- a/arch/arm/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/dts/sunxi-h3-h5.dtsi
> @@ -567,9 +567,14 @@
> };
>
> mbus: dram-controller@1c62000 {
> - compatible = "allwinner,sun8i-h3-mbus";
> - reg = <0x01c62000 0x1000>;
> - clocks = <&ccu CLK_MBUS>;
> + /* compatible is in per SoC .dtsi file */
> + reg = <0x01c62000 0x1000>,
> + <0x01c63000 0x1000>;
> + reg-names = "mbus", "dram";
> + clocks = <&ccu CLK_MBUS>,
> + <&ccu CLK_DRAM>,
> + <&ccu CLK_BUS_DRAM>;
> + clock-names = "mbus", "dram", "bus";
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x00000000 0x40000000 0xc0000000>;
> @@ -812,8 +817,8 @@
> reg-io-width = <1>;
> interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> - <&ccu CLK_HDMI>;
> - clock-names = "iahb", "isfr", "tmds";
> + <&ccu CLK_HDMI>, <&rtc 0>;
> + clock-names = "iahb", "isfr", "tmds", "cec";
> resets = <&ccu RST_BUS_HDMI1>;
> reset-names = "ctrl";
> phys = <&hdmi_phy>;
> @@ -859,6 +864,15 @@
> #clock-cells = <1>;
> };
>
> + r_intc: interrupt-controller@1f00c00 {
> + compatible = "allwinner,sun8i-h3-r-intc",
> + "allwinner,sun6i-a31-r-intc";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x01f00c00 0x400>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> r_ccu: clock@1f01400 {
> compatible = "allwinner,sun8i-h3-r-ccu";
> reg = <0x01f01400 0x100>;
> @@ -897,6 +911,19 @@
> #size-cells = <0>;
> };
>
> + r_uart: serial@1f02800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01f02800 0x400>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&r_ccu CLK_APB0_UART>;
> + resets = <&r_ccu RST_APB0_UART>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_uart_pins>;
> + status = "disabled";
> + };
> +
> r_pio: pinctrl@1f02c00 {
> compatible = "allwinner,sun8i-h3-r-pinctrl";
> reg = <0x01f02c00 0x400>;
> @@ -922,6 +949,11 @@
> pins = "PL10";
> function = "s_pwm";
> };
> +
> + r_uart_pins: r-uart-pins {
> + pins = "PL2", "PL3";
> + function = "s_uart";
> + };
> };
>
> r_pwm: pwm@1f03800 {
> diff --git a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
> index 19b3b23cfa..9e14fe5fdc 100644
> --- a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
> +++ b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
> @@ -49,6 +49,7 @@
> label = "power";
> linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
> + wakeup-source;
> };
> };
>
> @@ -128,6 +129,18 @@
> cpu-supply = <&reg_vdd_cpux>;
> };
>
> +&cpu1 {
> + cpu-supply = <&reg_vdd_cpux>;
> +};
> +
> +&cpu2 {
> + cpu-supply = <&reg_vdd_cpux>;
> +};
> +
> +&cpu3 {
> + cpu-supply = <&reg_vdd_cpux>;
> +};
> +
> &de {
> status = "okay";
> };
> diff --git a/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi
> index 204fba3614..50d328c2a8 100644
> --- a/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi
> +++ b/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi
> @@ -156,7 +156,7 @@
> &spi0 {
> status = "okay";
>
> - spiflash@0 {
> + flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <50000000>;