From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34BA0C433F5 for ; Fri, 6 May 2022 09:06:50 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8E1CC84099; Fri, 6 May 2022 11:06:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="EqTykpF6"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C5D5781DD6; Fri, 6 May 2022 11:05:49 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6680B83AB7 for ; Fri, 6 May 2022 11:05:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C91CEB83470; Fri, 6 May 2022 09:05:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 327D5C385AA; Fri, 6 May 2022 09:05:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651827934; bh=znqPyVp2R8IlRfIKIVzaIjpf5Nw2pN6cDJLF2uwsbyg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EqTykpF6aS6zjTr7EuKCyfVSBTsmkVtlYWaz39hg7pK98KVwKsc84chpdMWdACnv6 7nCaOoxmCbubkd7GQhAo/002ZAw8N7H3QkGWLkwrNftwJYVePMZ2fyHi9hyJVN2gF+ 9YRHeaFuKWMXbxpnQBcbErljjFLbzo3Y/H5XRw67tM9UM3JahrXnNZeAaLq1AWJtSN ltrSL/0otrlnQn/+1mALW48Rv/Oq8NWdkGE63HDKMCADoWcQhRT4m6RNOUfxrw76T4 07uf5RGlNOmdB/H1kdQyhq/wWWxqwH3u6yAYO9oNIWPeAqoNo4OH/fgBkx3zkWDQqX /KegIXOp3OHcw== Received: by pali.im (Postfix) id B3BFA125F; Fri, 6 May 2022 11:05:31 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , Marek Behun Cc: u-boot@lists.denx.de Subject: [PATCH 2/5] arm: mvebu: Move internal registers in arch_very_early_init() function Date: Fri, 6 May 2022 11:05:14 +0200 Message-Id: <20220506090517.5935-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220506090517.5935-1-pali@kernel.org> References: <20220506090517.5935-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Moving of internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE needs to be done very early, prior calling any function which may touch internal registers, like debug_uart_init(). So do it earlier in arch_very_early_init() instead of arch_cpu_init(). Movement is done in proper U-Boot, not in SPL. SPL may return to bootrom and bootrom requires internal registers at (old) expected location. Signed-off-by: Pali Rohár --- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/cpu.c | 31 ------------------------------- arch/arm/mach-mvebu/lowlevel.S | 27 +++++++++++++++++++++++++++ 4 files changed, 29 insertions(+), 31 deletions(-) create mode 100644 arch/arm/mach-mvebu/lowlevel.S diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index a3f273f4f949..98b13d1e336d 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -16,6 +16,7 @@ config ARMADA_32BIT select SUPPORT_SPL select TRANSLATION_OFFSET select SPL_SYS_NO_VECTOR_TABLE if SPL + select ARCH_VERY_EARLY_INIT config ARMADA_64BIT bool diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 1b451889d242..8bd2246325ca 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -21,6 +21,7 @@ else # CONFIG_ARCH_KIRKWOOD obj-y = cpu.o obj-y += dram.o +obj-y += lowlevel.o obj-$(CONFIG_DM_RESET) += system-controller.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1e893777b292..173d95a760a3 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -413,20 +413,7 @@ static void update_sdram_window_sizes(void) } } -void mmu_disable(void) -{ - asm volatile( - "mrc p15, 0, r0, c1, c0, 0\n" - "bic r0, #1\n" - "mcr p15, 0, r0, c1, c0, 0\n"); -} - #ifdef CONFIG_ARCH_CPU_INIT -static void set_cbar(u32 addr) -{ - asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); -} - #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2)) #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \ @@ -476,24 +463,6 @@ int arch_cpu_init(void) struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - /* - * Only with disabled MMU its possible to switch the base - * register address on Armada 38x. Without this the SDRAM - * located at >= 0x4000.0000 is also not accessible, as its - * still locked to cache. - */ - mmu_disable(); - - /* Linux expects the internal registers to be at 0xf1000000 */ - writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); - set_cbar(SOC_REGS_PHY_BASE + 0xC000); - - /* - * From this stage on, the SoC detection is working. As we have - * configured the internal register base to the value used - * in the macros / defines in the U-Boot header (soc.h). - */ - if (mvebu_soc_family() == MVEBU_SOC_A38X) { /* * To fully release / unlock this area from cache, we need diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S new file mode 100644 index 000000000000..2491310eb0c1 --- /dev/null +++ b/arch/arm/mach-mvebu/lowlevel.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include + +ENTRY(arch_very_early_init) +#ifdef CONFIG_ARMADA_38X + /* + * Only with disabled MMU its possible to switch the base + * register address on Armada 38x. Without this the SDRAM + * located at >= 0x4000.0000 is also not accessible, as its + * still locked to cache. + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, #1 + mcr p15, 0, r0, c1, c0, 0 +#endif + + /* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */ + ldr r0, =SOC_REGS_PHY_BASE + ldr r1, =INTREG_BASE_ADDR_REG + str r0, [r1] + add r0, r0, #0xC000 + mcr p15, 4, r0, c15, c0 + + bx lr +ENDPROC(arch_very_early_init) -- 2.20.1