From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31509C433EF for ; Mon, 9 May 2022 12:17:38 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1819384099; Mon, 9 May 2022 14:16:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Lpw3FqCJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AB40C83E0F; Mon, 9 May 2022 08:20:41 +0200 (CEST) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BD49B83DFE for ; Mon, 9 May 2022 08:20:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vaishnav.a@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2496KZxf121253; Mon, 9 May 2022 01:20:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1652077235; bh=pvaEpbhRKfVsGsobfq4A0N8OGbcfy6MWJgdT3roHBI4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Lpw3FqCJUXaPMNYe/4baxPFX6CbnYui145FhdbUfQX72cJdlC36oMsdN2La1IFMjS hmegcHHGDFXfxbErs8Bi+oACVgoIafHN/oD+Uf7VeXMvyIN0o+MFrjOpepPFsKvOm+ 9CO4gxTfNhF3RWin38wp2JavQKRwpEAf86nZ469Y= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2496KZgC020608 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 May 2022 01:20:35 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 9 May 2022 01:20:34 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 9 May 2022 01:20:34 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2496KXF5015774; Mon, 9 May 2022 01:20:34 -0500 From: Vaishnav Achath To: , , , , , , , CC: Subject: [PATCH 8/9] ti: j721e: enable hyperflash spl fixup for j721e Date: Mon, 9 May 2022 11:50:16 +0530 Message-ID: <20220509062017.27623-9-vaishnav.a@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220509062017.27623-1-vaishnav.a@ti.com> References: <20220509062017.27623-1-vaishnav.a@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Approved-At: Mon, 09 May 2022 14:15:58 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On j721e, its not possible to use OSPI0 and HBMC simultaneously as they are muxed within the Flash Subsystem hence disable HBMC by default and keep OSPI enabled. Bootloader will fixup DT when it detects HyperFlash mux selection instead of OSPI. Also updated detect_enable_hyperflash to use correct GPIO when checking hypermux selection state: * J7200 - hypermux sel connected to WKUP_GPIO0_6 * J721E - hypermux·sel·connected·to·WKUP_GPIO0_8 Signed-off-by: Vaishnav Achath --- board/ti/j721e/evm.c | 57 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 54 insertions(+), 3 deletions(-) diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index e6ff54c065..105461e1db 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -109,11 +109,12 @@ int board_fit_config_name_match(const char *name) static void __maybe_unused detect_enable_hyperflash(void *blob) { struct gpio_desc desc = {0}; + char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6"; - if (dm_gpio_lookup_name("6", &desc)) + if (dm_gpio_lookup_name(hypermux_sel_gpio, &desc)) return; - if (dm_gpio_request(&desc, "6")) + if (dm_gpio_request(&desc, hypermux_sel_gpio)) return; if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN)) @@ -132,7 +133,8 @@ static void __maybe_unused detect_enable_hyperflash(void *blob) } #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM) +#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \ + defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM)) void spl_perform_fixups(struct spl_image_info *spl_image) { detect_enable_hyperflash(spl_image->fdt_addr); @@ -490,6 +492,41 @@ int board_late_init(void) } #endif +static int __maybe_unused detect_SW3_1_state(void) +{ + if (IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) { + struct gpio_desc desc = {0}; + int ret; + char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6"; + + ret = dm_gpio_lookup_name(hypermux_sel_gpio, &desc); + if (ret) { + printf("error getting GPIO lookup name: %d\n", ret); + return ret; + } + + ret = dm_gpio_request(&desc, hypermux_sel_gpio); + if (ret) { + printf("error requesting GPIO: %d\n", ret); + goto err_free_gpio; + } + + ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + if (ret) { + printf("error setting direction flag of GPIO: %d\n", ret); + goto err_free_gpio; + } + + ret = dm_gpio_get_value(&desc); + if (ret < 0) + printf("error getting value of GPIO: %d\n", ret); + +err_free_gpio: + dm_gpio_free(desc.dev, &desc); + return ret; + } +} + void spl_board_init(void) { #if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC) @@ -522,4 +559,18 @@ void spl_board_init(void) printf("ESM PMIC init failed: %d\n", ret); } #endif + if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) && + IS_ENABLED(CONFIG_HBMC_AM654)) { + struct udevice *dev; + int ret; + + ret = detect_SW3_1_state(); + if (ret == 1) { + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(hbmc_am654), + &dev); + if (ret) + debug("Failed to probe hyperflash\n"); + } + } } -- 2.17.1