From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC6BCC433F5 for ; Mon, 9 May 2022 17:02:57 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 91FC883F34; Mon, 9 May 2022 19:02:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=pschenker.ch Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=pschenker.ch header.i=@pschenker.ch header.b="BPYY5oBY"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7203E83E14; Mon, 9 May 2022 18:59:06 +0200 (CEST) Received: from smtp-190b.mail.infomaniak.ch (smtp-190b.mail.infomaniak.ch [IPv6:2001:1600:3:17::190b]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2F60283EB7 for ; Mon, 9 May 2022 18:59:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=pschenker.ch Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dev@pschenker.ch Received: from smtp-3-0001.mail.infomaniak.ch (unknown [10.4.36.108]) by smtp-2-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4KxnSh52nXzMqBt5; Mon, 9 May 2022 18:59:00 +0200 (CEST) Received: from localhost.localdomain (unknown [31.10.206.125]) by smtp-3-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4KxnSh3YsvzlhMC1; Mon, 9 May 2022 18:59:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=pschenker.ch; s=20220412; t=1652115540; bh=C5lczsfm4mSTKrlhQEalnRFidwrhftM23+9KPzpfg2E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BPYY5oBYJ0PGC4oei2pMzSHxgzq7iO/GI8gSBtZToffVoCRDMfMjZ2gEkK6SSEOtv zncka1Ol+HzchL1fpRGI4YiVSVlJ5tdJGiEj9hEzqXIuzs6eF1e7wyIxka713H6Ck6 vfh4dGMIBoYwlf7jQe1CK9ZM+4T6djM35znuQJrQ= From: Philippe Schenker To: Marcel Ziswiler , u-boot@lists.denx.de Cc: Philippe Schenker , Francesco Dolcini Subject: [PATCH 2/2] board: apalis-imx8: add new 8gb product variant Date: Mon, 9 May 2022 18:58:16 +0200 Message-Id: <20220509165816.279617-2-dev@pschenker.ch> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220509165816.279617-1-dev@pschenker.ch> References: <20220509165816.279617-1-dev@pschenker.ch> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Mon, 09 May 2022 19:02:39 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Philippe Schenker Add the new Apalis iMX8 product variant 0067: Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT the only difference to the product 0037 Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT is the 8gb of RAM. Toradex strategy to choose the correct RAM timing in SCFW is by fuses in the user area telling which RAM timing to load. This commit makes use of this information to set the correct size of the RAM and therefore distinguish between the new 0067 and 0037 product Signed-off-by: Philippe Schenker Reviewed-by: Francesco Dolcini --- board/toradex/apalis-imx8/apalis-imx8.c | 81 +++++++++++++++++++++++-- 1 file changed, 77 insertions(+), 4 deletions(-) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 04877fcd94..408198843f 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/tdx-cfg-block.h" @@ -28,22 +29,75 @@ DECLARE_GLOBAL_DATA_PTR; (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#define TDX_USER_FUSE_BLOCK1_A 276 +#define TDX_USER_FUSE_BLOCK1_B 277 +#define TDX_USER_FUSE_BLOCK2_A 278 +#define TDX_USER_FUSE_BLOCK2_B 279 + static iomux_cfg_t uart1_pads[] = { SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +struct tdx_user_fuses { + u16 pid4; + u16 vers; + u8 ramid; +}; + static void setup_iomux_uart(void) { imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +static uint32_t do_get_tdx_user_fuse(int a, int b) +{ + sc_err_t sciErr; + u32 val_a = 0; + u32 val_b = 0; + + sciErr = sc_misc_otp_fuse_read(-1, a, &val_a); + if (sciErr != SC_ERR_NONE) { + printf("Error reading out user fuse %d\n", a); + return 0; + } + + sciErr = sc_misc_otp_fuse_read(-1, b, &val_b); + if (sciErr != SC_ERR_NONE) { + printf("Error reading out user fuse %d\n", b); + return 0; + } + + return ((val_a & 0xffff) << 16) | (val_b & 0xffff); +} + +static void get_tdx_user_fuse(struct tdx_user_fuses *tdxuserfuse) +{ + u32 fuse_block; + + fuse_block = do_get_tdx_user_fuse(TDX_USER_FUSE_BLOCK2_A, + TDX_USER_FUSE_BLOCK2_B); + + /* + * Fuse block 2 acts as a backup area, if this reads 0 we want to + * use fuse block 1 + */ + if (fuse_block == 0) + fuse_block = do_get_tdx_user_fuse(TDX_USER_FUSE_BLOCK1_A, + TDX_USER_FUSE_BLOCK1_B); + + tdxuserfuse->pid4 = (fuse_block >> 18) & GENMASK(13, 0); + tdxuserfuse->vers = (fuse_block >> 4) & GENMASK(13, 0); + tdxuserfuse->ramid = fuse_block & GENMASK(3, 0); +} + void board_mem_get_layout(u64 *phys_sdram_1_start, u64 *phys_sdram_1_size, u64 *phys_sdram_2_start, u64 *phys_sdram_2_size) { u32 is_quadplus = 0, val = 0; + struct tdx_user_fuses tdxramfuses; sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); if (scierr == SC_ERR_NONE) { @@ -51,14 +105,33 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, is_quadplus = ((val >> 4) & 0x3) != 0x0; } + get_tdx_user_fuse(&tdxramfuses); + *phys_sdram_1_start = PHYS_SDRAM_1; *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; *phys_sdram_2_start = PHYS_SDRAM_2; - if (is_quadplus) - /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */ + + switch (tdxramfuses.ramid) { + case 1: + *phys_sdram_2_size = SZ_2G; + break; + case 2: *phys_sdram_2_size = 0x0UL; - else - *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; + break; + case 3: + *phys_sdram_2_size = SZ_2G; + break; + case 4: + *phys_sdram_2_size = SZ_4G + SZ_2G; + break; + default: + if (is_quadplus) + /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */ + *phys_sdram_2_size = 0x0UL; + else + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; + break; + } } int board_early_init_f(void) -- 2.35.1