[PULL] u-boot-riscv/master

Leo Liang
2023-02-02T06:30:33Z

Hi Tom,

The following changes since commit 73a3f5139182a0389d505bf29b0ad4bc29424cf8:

Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-01-31 18:28:07 -0500)

are available in the Git repository at:

https://source.denx.de/u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 2b0af9feb594b68a75e4f111bde7f55ddb14995d:

board: sifive: unmatched: enable booting on a second NVME device (2023-02-01 16:17:59 +0800)

CI result show no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15011

----------------------------------------------------------------
+ riscv lib:
+ optimize memcpy for "dst == src" case
+ check if u-mode exists before writing mcounteren register
+ unmatched board config: enable second NVME device on unmatched board
+ ae350 board:
+ Adjust memory layout and some CSR setting
----------------------------------------------------------------
Aurelien Jarno (1):
board: sifive: unmatched: enable booting on a second NVME device

Nikita Shubin (1):
riscv: cpu: check U-Mode before counteren write

Rick Chen (4):
riscv: ae350: Enable CCTL_SUEN
riscv: ax25: bypass malloc when spl fit boots from ram
riscv: memcpy: check src and dst before copy
riscv: ae350: support OpenSBI 1.0+ which enable FW_PIC

arch/riscv/cpu/ax25/Makefile | 1 +
arch/riscv/cpu/ax25/cpu.c | 18 +++++++++++-------
arch/riscv/cpu/ax25/spl.c | 27 +++++++++++++++++++++++++++
arch/riscv/cpu/cpu.c | 16 ++++++++--------
arch/riscv/lib/memcpy.S | 2 ++
board/AndesTech/ax25-ae350/Kconfig | 2 +-
include/configs/sifive-unmatched.h | 1 +
7 files changed, 51 insertions(+), 16 deletions(-)
create mode 100644 arch/riscv/cpu/ax25/spl.c

Best regards,
Leo