From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D9C7C433EF for ; Fri, 10 Jun 2022 16:48:23 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9C23E8431E; Fri, 10 Jun 2022 18:48:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinet.cat Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 81E9984407; Fri, 10 Jun 2022 18:48:19 +0200 (CEST) Received: from mx1.tinet.cat (mx1.tinet.org [195.77.216.146]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AE78D83B68 for ; Fri, 10 Jun 2022 18:48:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinet.cat Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=xdrudis@tinet.cat X-ASG-Debug-ID: 1654879695-163e7b45506aada0001-4l7tJC Received: from smtp01.tinet.cat (smtp01.tinet.org [195.77.216.131]) by mx1.tinet.cat with ESMTP id urVENbiOlP87E1Vp; Fri, 10 Jun 2022 18:48:15 +0200 (CEST) X-Barracuda-Envelope-From: xdrudis@tinet.cat X-Barracuda-Effective-Source-IP: smtp01.tinet.org[195.77.216.131] X-Barracuda-Apparent-Source-IP: 195.77.216.131 Received: from begut (50.red-79-152-182.dynamicip.rima-tde.net [79.152.182.50]) by smtp01.tinet.cat (Postfix) with ESMTPSA id 39D9C6063587; Fri, 10 Jun 2022 18:48:15 +0200 (CEST) Date: Fri, 10 Jun 2022 18:48:13 +0200 From: Xavier Drudis Ferran To: Stefan Herbrechtsmeier Cc: Michal Simek , U-Boot , Stefan Herbrechtsmeier , Michal Simek Subject: Re: [SPAM] Re: [PATCH v2] xilinx: zynqmp: Do not use 0 as spl bss start address Message-ID: <20220610164813.GE1735@begut> X-ASG-Orig-Subj: Re: [SPAM] Re: [PATCH v2] xilinx: zynqmp: Do not use 0 as spl bss start address References: <20220607074314.27125-1-stefan.herbrechtsmeier-oss@weidmueller.com> <25751198-541e-9fa0-a23a-db0069eb9327@weidmueller.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <25751198-541e-9fa0-a23a-db0069eb9327@weidmueller.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-Barracuda-Connect: smtp01.tinet.org[195.77.216.131] X-Barracuda-Start-Time: 1654879695 X-Barracuda-URL: https://webmail.tinet.cat:443/cgi-mod/mark.cgi X-Barracuda-Scan-Msg-Size: 2144 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: SPAM GLOBAL 1.0000 1.0000 4.3430 X-Barracuda-Spam-Score: 4.34 X-Barracuda-Spam-Status: No, SCORE=4.34 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=6.0 KILL_LEVEL=8.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.98620 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean El Fri, Jun 10, 2022 at 04:42:55PM +0200, Stefan Herbrechtsmeier deia: > Hi Michal, > > what is the default entry address for the aft / bl31.bin? > > I have a bl31.bin with an entry address of 0x1000 and this is inside the > BSS. > Me too, load address at 0x1000, but for me in SPL text, not BSS. I have a litle customized, a little old TF-A for rk3399 / Rock pi 4 loading at address 0 with entry at 0x1000. But include/configs/rk3399_common.h sets my CONFIG_SPL_BSS_START_ADDR=0x400000, away from harm. I had problems booting anyway. Now I can load U-Boot from MMC with these patches https://lists.denx.de/pipermail/u-boot/2022-June/485497.html In particular CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x15000 This is defined in arch/arm/mach-rockchip/Kconfig and says it's to avoid conflicts with SPL text area, not BSS But I found other boards with CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000, so I thought some low addresses where normal. I don't know. I had to modify the code loading from SPI because, unlike MMC code, it thought address 0 meant no destination (I can send those patches when I have them cleaner if anyone wants them). I just realised that I have CONFIG_SPL_TEXT_BASE=0x0. I'm not finding where that's defined, maybe it's simply because it's not defined anywhere, so maybe the solution for me would be setting CONFIG_SPL_TEXT_BASE to 0x10000000 or something. Or maybe it needs to be at 0x0 because it is bootrom who is loading it, and it won't look where I define it? I can't remember whether I tried this. Maybe you can try to look at the size of a file bl31_0x00000000.bin that is generated when you build U-boot with BL31 pointing at your bl31.elf (check u-boot.its if that's not the name for you). Then set CONFIG_SPL_BSS_START_ADDR to that size + L (L= value of load property in entry atf_1 of u-boot.its). This should leave a hole at the beginning of U-Boot to make room for your TF-A, and leave BSS elsewhere. The sources and build scripts for TF-A are public, so maybe one could look at what's the criteria for putting images at different addresses?