From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9362C43334 for ; Tue, 14 Jun 2022 15:23:07 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 68C038425C; Tue, 14 Jun 2022 17:23:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="lfUL01SE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 52C8880112; Tue, 14 Jun 2022 16:45:58 +0200 (CEST) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 443C680112 for ; Tue, 14 Jun 2022 16:45:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=g-vlaev@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 25EEjpZs045801; Tue, 14 Jun 2022 09:45:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1655217951; bh=FqoDvckwNPDww6lr1lNXGRsC49kavPGtCQUbtmg7noY=; h=From:To:CC:Subject:Date; b=lfUL01SEqqyhV1oevMx7l5i3TJC71JJe14//fURuvQqRLvkbv6vDENM0VIAeHDPjy p1C948FbZ6KbZZ9jBgEY9KkrAMlmzCUfiFccwNjWzrA0W51U0M7yqZ68Xs/L19WqU/ +ujwBDgQgiyxn7wVWL2W5fdl0mCpgZmJf0HBi/mg= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 25EEjpEo012513 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 14 Jun 2022 09:45:51 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 14 Jun 2022 09:45:51 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 14 Jun 2022 09:45:51 -0500 Received: from jti.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 25EEjiE3066960; Tue, 14 Jun 2022 09:45:47 -0500 From: Georgi Vlaev To: Vignesh Raghavendra , Anand Gadiyar , Tom Rini CC: , Georgi Vlaev Subject: [PATCH 0/5] board: ti: am62x: Add support for 1-bit inline DDRSS ECC Date: Tue, 14 Jun 2022 17:45:29 +0300 Message-ID: <20220614144534.317407-1-g-vlaev@ti.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Approved-At: Tue, 14 Jun 2022 17:23:03 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi, This series enables the 1-bit inline DDR ECC support in the TI DDRSS bridge for AM62x. The base DDRSS ECC support was merged for k3-ddrss in a previous series for AM64x [1]. The ECC data is stored together with the data, which will reduce the total available memory with 1/9th. The k3-ddrss driver enables the ECC support and primes the full memory from the R5 SPL, so the the memory size changes must propagate from the R5 SPL to A53 SPL and then to A53 u-boot. The patches are similar to those we have for AM64x, with one exception: "arm: mach-k3: common: Use ddr_init in spl_enable_dcache". Since we've switched the boards to DT to fetch the memory configuration, dram_init_banksize() will no longer set the total memory size in the global data. And spl_enable_dcache() uses dram_init_banksize() instead of dram_init(), which actually sets the memory base/size. Note this doesn't enable the 1-bit ECC on any platform by default. This can be done by adding the "ti,ecc-enable" property to the memorycontroller node in k3-am6*-ddr.dtsi. [1] https://lore.kernel.org/u-boot/20220317170346.31162-1-d-gerlach@ti.com/ The patches depend on the base AM62 support, which was recently merged in u-boot/next. Georgi Vlaev (5): arm: mach-k3: common: Use ddr_init in spl_enable_dcache arm: dts: k3-am625-*: Mark memory with u-boot,dm-spl board: ti: am62x: Use fdt functions for ram and bank init board: ti: am62x: Account for DDR size fixups if ECC is enabled configs: am62x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig arch/arm/dts/k3-am625-r5-sk.dts | 1 + arch/arm/dts/k3-am625-sk-u-boot.dtsi | 4 ++ arch/arm/mach-k3/common.c | 2 +- board/ti/am62x/evm.c | 62 ++++++++++++++++++++++++---- configs/am62x_evm_r5_defconfig | 1 + 5 files changed, 61 insertions(+), 9 deletions(-) base-commit: a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74 -- 2.30.2