From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D340C43334 for ; Tue, 14 Jun 2022 15:23:18 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 89BC584334; Tue, 14 Jun 2022 17:23:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="X6oE60ln"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0E90880112; Tue, 14 Jun 2022 16:46:04 +0200 (CEST) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6037F83EDC for ; Tue, 14 Jun 2022 16:46:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=g-vlaev@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 25EEjxP6029243; Tue, 14 Jun 2022 09:45:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1655217959; bh=ls/+0vRKp999d0XGQflNQjUhVKh876KeVonRzaqHIow=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X6oE60ln44PFDmq1/JNlJg06Sz6NAl1PT9p4TTirnQ2N7JvBQDzSwqCV0chkKXjr3 kdLUE0Snydhiz3T0vqk3kmQu6+Ljg0CkwcXl6usGFaNwxsEYBw7UR69QHv/2WFQ+mF oY7uA50aloZo3+ibif9w7ygumBL01eOf8ZvigUYo= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 25EEjxZP127350 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 14 Jun 2022 09:45:59 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 14 Jun 2022 09:45:58 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 14 Jun 2022 09:45:58 -0500 Received: from jti.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 25EEjiE4066960; Tue, 14 Jun 2022 09:45:52 -0500 From: Georgi Vlaev To: Vignesh Raghavendra , Anand Gadiyar , Tom Rini CC: , Georgi Vlaev Subject: [PATCH 1/5] arm: mach-k3: common: Use ddr_init in spl_enable_dcache Date: Tue, 14 Jun 2022 17:45:30 +0300 Message-ID: <20220614144534.317407-2-g-vlaev@ti.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220614144534.317407-1-g-vlaev@ti.com> References: <20220614144534.317407-1-g-vlaev@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Approved-At: Tue, 14 Jun 2022 17:23:03 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The spl_enable_dcache() function calls dram_init_banksize() to get the total memory size. Normally the dram_init_banksize() setups the memory banks, while the total size is reported by ddr_init(). This worked so far for K3 since we set the gd->ram_size in dram_init_banksize() as well. Signed-off-by: Georgi Vlaev --- arch/arm/mach-k3/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index b4b75f4e6c86..70f6444e7988 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -516,7 +516,7 @@ void spl_enable_dcache(void) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; - dram_init_banksize(); + dram_init(); /* reserve TLB table */ gd->arch.tlb_size = PGTABLE_SIZE; -- 2.30.2