From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1315DC433EF for ; Tue, 14 Jun 2022 15:23:49 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B0D6F8438F; Tue, 14 Jun 2022 17:23:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="YaPUsfuN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 09F2584284; Tue, 14 Jun 2022 16:46:20 +0200 (CEST) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7199A80112 for ; Tue, 14 Jun 2022 16:46:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=g-vlaev@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 25EEkFAt012518; Tue, 14 Jun 2022 09:46:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1655217975; bh=kX1CcCFotbmE8RFc/7EiRNQhGoO3wRGnjtK16F6+Nsg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YaPUsfuNAWfBFM5olKrXXtRaH4nvDpotigKC0KBgKSfna2esbCAJhk6fuEKqmUlJv h8TE5nevXtO4Tg3VziPA+3HVzLLUxqaxC2IyTw9/648nIqy1IvsqaKKqeoHxYKHbYo Xf5T5s9wDFUvoGuEfVbZftS49wHEB6sNnNUEHbdI= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 25EEkF6S019910 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 14 Jun 2022 09:46:15 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 14 Jun 2022 09:46:15 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 14 Jun 2022 09:46:15 -0500 Received: from jti.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 25EEjiE7066960; Tue, 14 Jun 2022 09:46:11 -0500 From: Georgi Vlaev To: Vignesh Raghavendra , Anand Gadiyar , Tom Rini CC: , Georgi Vlaev Subject: [PATCH 4/5] board: ti: am62x: Account for DDR size fixups if ECC is enabled Date: Tue, 14 Jun 2022 17:45:33 +0300 Message-ID: <20220614144534.317407-5-g-vlaev@ti.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220614144534.317407-1-g-vlaev@ti.com> References: <20220614144534.317407-1-g-vlaev@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Approved-At: Tue, 14 Jun 2022 17:23:03 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Call into k3-ddrss driver to fixup device tree and resize the available amount of DDR if ECC is enabled. A second fixup is required from A53 SPL to take the fixup as done from R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes this to the OS. Signed-off-by: Georgi Vlaev --- board/ti/am62x/evm.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index fb5106d1f3c8..d65ee1d69606 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -9,6 +9,8 @@ #include #include +#include +#include #include #include #include @@ -30,3 +32,54 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_K3_AM64_DDRSS) +static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{ + struct udevice *dev; + int ret; + + dram_init_banksize(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("Cannot get RAM device for ddr size fixup: %d\n", ret); + + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node for ECC use! %d\n", ret); +} +#else +static void fixup_memory_node(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, + CONFIG_NR_DRAM_BANKS); + if (ret) + printf("Error fixing up memory node! %d\n", ret); +} +#endif + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ +#if defined(CONFIG_K3_AM64_DDRSS) + fixup_ddr_driver_for_ecc(spl_image); +#else + fixup_memory_node(spl_image); +#endif +} +#endif -- 2.30.2