From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B125C43334 for ; Thu, 23 Jun 2022 16:23:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4C4EA842D4; Thu, 23 Jun 2022 18:23:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="qFwgur8l"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B955F842D4; Thu, 23 Jun 2022 18:23:20 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4CD5C83DFB for ; Thu, 23 Jun 2022 18:23:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E3EA0B8247D; Thu, 23 Jun 2022 16:23:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4CE68C3411B; Thu, 23 Jun 2022 16:23:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656001396; bh=E07WWrQSkffIBzcsDm8M5cOEA+bTBEV44weZpAcFxjY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qFwgur8lPHrdSDlle2qsmzNrwa2fKCNuELRZ/LtV1YAWqa8JAmBYrR9/1A33q274D Ko4suAUSlZB07/EBQsVaWu7SuYUj2ukf24KkATDTTftNnLzXXemaIl+V9ttZpDfMDW rbkIeMfZbXXFIRiUO2K8CH7bF4CY2dmnODdTqqoStE5KRPpQBNLKAUorPCu0STHPB2 1vhaxaTCN5fpztdfcxCp7Ofm35xgV/r3tEI2R0+BZMZ9Wyk6hmA734e4hwS/2oVc93 oE4WJaZlJs+SKlxgEMrrLQ4bxVM9j5zPvNLzRgHKy60140id6b4enQGCBZilEAZnOb FSFb3Nab5CrTg== Received: by pali.im (Postfix) id 4760C79F; Thu, 23 Jun 2022 18:23:13 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , "Peng Fan (OSS)" Cc: u-boot@lists.denx.de Subject: [PATCH v2] board: freescale: p1_p2_rdb_pc: Remove mapping for TDM-PMC card Date: Thu, 23 Jun 2022 18:22:21 +0200 Message-Id: <20220623162221.14968-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220427141317.18962-1-pali@kernel.org> References: <20220427141317.18962-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean >From whole P1/P2 family of RDB boards is TDM-PMC card (PCI Mezzanine Card, Freescale PQ-MDS-T1) available only on P1021RDB and P1025RDB boards. So address mapping for TDM-PMC card on LBC should not be enabled on any other P1/P2 RDB board as there is no device at that TDM-PMC address. Support for P1021RDB and P1025RDB boards was already removed from mainline U-Boot in commits 6d1dd76afe85 ("board/freescale: Remove P1021RDB board support") and d521cece5adb ("board/freescale: Remove P1025RDB board support"). So do not enable TDM-PMC address mapping on remaining P1/P2 RDB boards and remove all macros related to TDM-PMC address mappings. Signed-off-by: Pali Rohár --- Changes in v2: * Rebase on top of next branch, commit 9121478ee6f2aee381f8fe49d8997d43527d351a --- board/freescale/p1_p2_rdb_pc/law.c | 1 - board/freescale/p1_p2_rdb_pc/tlb.c | 3 --- include/configs/p1_p2_rdb_pc.h | 9 --------- scripts/config_whitelist.txt | 4 ---- 4 files changed, 17 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 5f4d713ca569..6bdfb356eede 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -9,7 +9,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 6ded38ac683e..38843a96cbfb 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -65,9 +65,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_64K, 1), #endif /* not SPL */ #ifdef CONFIG_SYS_NAND_BASE diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 56a16502dcc7..f95a77b7ed32 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -182,7 +182,6 @@ * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable * (early boot only) * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 - * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable @@ -289,14 +288,6 @@ #endif /* CPLD config size: 1Mb */ -#define CONFIG_SYS_PMC_BASE 0xff980000 -#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE -#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ - BR_PS_8 | BR_V) -#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ - OR_GPCM_EAD) - /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define __VSCFW_ADDR "vscfw_addr=ef000000\0" diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 726973b26e21..7fed8b612bd7 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -456,8 +456,6 @@ CONFIG_PHY_IRAM_BASE CONFIG_PL011_CLOCK CONFIG_PL01x_PORTS CONFIG_PM -CONFIG_PMC_BR_PRELIM -CONFIG_PMC_OR_PRELIM CONFIG_PME_PLAT_CLK_DIV CONFIG_POST CONFIG_POSTBOOTMENU @@ -1465,8 +1463,6 @@ CONFIG_SYS_PLL_FDR CONFIG_SYS_PLL_ODR CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_PMAN -CONFIG_SYS_PMC_BASE -CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PME_CLK CONFIG_SYS_POST_MEMORY CONFIG_SYS_POST_MEM_REGIONS -- 2.20.1