From: Andre Przywara <andre.przywara@arm.com>
To: Chen-Yu Tsai <wens@kernel.org>
Cc: qianfan <qianfanguijin@163.com>,
U-Boot Mailing List <u-boot@lists.denx.de>,
Jagan Teki <jagan@amarulasolutions.com>,
Maxime Ripard <maxime@cerno.tech>,
Peter Robinson <pbrobinson@gmail.com>
Subject: Re: [PATCH v2] sunxi: psci: Fix sunxi_power_switch on sun8i-r40 platform
Date: Mon, 27 Jun 2022 01:16:21 +0100 [thread overview]
Message-ID: <20220627011621.5d5e335f@slackpad.lan> (raw)
In-Reply-To: <CAGb2v65AMssMV=QkdLVqOAXHN=VxMJ=RDbceReZ-LoUg6XoeMg@mail.gmail.com>
On Sat, 14 May 2022 11:52:01 +0800
Chen-Yu Tsai <wens@kernel.org> wrote:
Hi,
> On Sat, May 14, 2022 at 11:19 AM <qianfanguijin@163.com> wrote:
> >
> > From: qianfan Zhao <qianfanguijin@163.com>
> >
> > linux system will die if we offline one of the cpu on R40 based board:
> > eg: echo 0 > /sys/devices/system/cpu/cpu3/online
> >
> > Fixed sunxi_power_switch based on allwinner lichee 3.10 kernel driver.
> >
> > Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
>
> Please add a Fixes tag.
>
> > ---
> > v2 changes: Fix the commit message, the source code doesn't change.
> >
> > arch/arm/cpu/armv7/sunxi/psci.c | 24 +++++++++++++++++++-----
> > 1 file changed, 19 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
> > index 1ac50f558a..63186a9388 100644
> > --- a/arch/arm/cpu/armv7/sunxi/psci.c
> > +++ b/arch/arm/cpu/armv7/sunxi/psci.c
> > @@ -79,8 +79,7 @@ static void __secure __mdelay(u32 ms)
> > static void __secure clamp_release(u32 __maybe_unused *clamp)
> > {
> > #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
> > - defined(CONFIG_MACH_SUN8I_H3) || \
> > - defined(CONFIG_MACH_SUN8I_R40)
> > + defined(CONFIG_MACH_SUN8I_H3)
> > u32 tmp = 0x1ff;
> > do {
> > tmp >>= 1;
> > @@ -88,15 +87,30 @@ static void __secure clamp_release(u32 __maybe_unused *clamp)
> > } while (tmp);
> >
> > __mdelay(10);
> > +#elif defined(CONFIG_MACH_SUN8I_R40)
> > + u8 i, tmp = 0xfe;
> > +
> > + for (i = 0; i < 5; i++) { /* 0xfe, 0xf8, 0xe0, 0x80, 0x00 */
> > + writel(tmp, clamp);
> > + tmp <<= 2;
> > + }
> > +
> > + while (0x00 != readl(clamp)) {
> > + ;
> > + }
> > #endif
> > }
> >
> > static void __secure clamp_set(u32 __maybe_unused *clamp)
> > {
> > #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
> > - defined(CONFIG_MACH_SUN8I_H3) || \
> > - defined(CONFIG_MACH_SUN8I_R40)
> > + defined(CONFIG_MACH_SUN8I_H3)
> > writel(0xff, clamp);
> > +#elif defined(CONFIG_MACH_SUN8I_R40)
> > + writel(0xff, clamp);
> > + while (0xff != readl(clamp)) {
> > + ;
> > + }
> > #endif
> > }
> >
> > @@ -153,7 +167,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
> >
> > sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
> > (void *)cpucfg + SUN8I_R40_PWROFF,
> > - on, 0);
> > + on, cpu);
>
> I think this is the only change that is needed. Looking again at the
> R40 user manual, the original code turned off core 0 regardless of
> which core was being brought down.
Reduced the patch to this one change, adjusted and extended the commit
message, and applied to sunxi/master, for v2022.07.
Thanks,
Andre
>
> Could you give that a try? The power clamp stuff shouldn't change
> much, as the end result is the same. The readback might make a
> difference, but if it does, it should be applied to all SoCs.
>
>
> Regards
> ChenYu
>
> > }
> > #else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
> > static void __secure sunxi_cpu_set_power(int cpu, bool on)
> > --
> > 2.25.1
> >
prev parent reply other threads:[~2022-06-27 0:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-14 3:19 [PATCH v2] sunxi: psci: Fix sunxi_power_switch on sun8i-r40 platform qianfanguijin
2022-05-14 3:52 ` Chen-Yu Tsai
2022-05-14 5:08 ` qianfan
2022-06-25 0:51 ` Andre Przywara
2022-07-02 9:02 ` qianfan
2022-06-27 0:16 ` Andre Przywara [this message]
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