From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33958C43334 for ; Tue, 28 Jun 2022 00:43:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7DB3E84312; Tue, 28 Jun 2022 02:43:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2E160843D0; Tue, 28 Jun 2022 02:43:21 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 240A683EC5 for ; Tue, 28 Jun 2022 02:43:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 79A181691; Mon, 27 Jun 2022 17:43:17 -0700 (PDT) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D86EA3F66F; Mon, 27 Jun 2022 17:43:15 -0700 (PDT) Date: Tue, 28 Jun 2022 01:34:51 +0100 From: Andre Przywara To: qianfanguijin@163.com, Jagan Teki Cc: u-boot@lists.denx.de, Chen-Yu Tsai , Maxime Ripard , Samuel Holland , Simon Glass Subject: Re: [PATCH v1] drivers: spi: sunxi: Fix spi speed settting Message-ID: <20220628013451.4d452a16@slackpad.lan> In-Reply-To: <20220609090939.25828-1-qianfanguijin@163.com> References: <20220609090939.25828-1-qianfanguijin@163.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Thu, 9 Jun 2022 17:09:39 +0800 qianfanguijin@163.com wrote: Hi Qianfan, > From: qianfan Zhao > > dm_spi_claim_bus run spi_set_speed_mode first and then ops->claim_bus, > but spi clock is enabled when sun4i_spi_claim_bus, that will make > sun4i_spi_set_speed doesn't work. Thanks for bringing this up, and sorry for the delay (please CC: the U-Boot sunxi maintainers!). So this is very similar to the patch as I sent earlier: https://lore.kernel.org/u-boot/20220503212040.27884-3-andre.przywara@arm.com/ Can you please check whether this works for you as well, then reply to that patch? I put my version of the patch plus more fixes and F1C100s support to: https://source.denx.de/u-boot/custodians/u-boot-sunxi/-/commits/next/ Also I am curious under what circumstances and on what board you saw the issue? In my case it was on the F1C100s, which has a higher base clock (200 MHz instead of 24 MHz), so everything gets badly overclocked. Thanks! Andre > Fix it. > > Signed-off-by: qianfan Zhao > --- > drivers/spi/spi-sunxi.c | 78 ++++++++++++++++------------------------- > 1 file changed, 30 insertions(+), 48 deletions(-) > > diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c > index b6cd7ddafa..1043cde976 100644 > --- a/drivers/spi/spi-sunxi.c > +++ b/drivers/spi/spi-sunxi.c > @@ -224,6 +224,7 @@ err_ahb: > static int sun4i_spi_claim_bus(struct udevice *dev) > { > struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); > + u32 div, reg; > int ret; > > ret = sun4i_spi_set_clock(dev->parent, true); > @@ -233,12 +234,38 @@ static int sun4i_spi_claim_bus(struct udevice *dev) > setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE | > SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP)); > > + /* Setup clock divider */ > + div = SUN4I_SPI_MAX_RATE / (2 * priv->freq); > + reg = readl(SPI_REG(priv, SPI_CCR)); > + > + if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { > + if (div > 0) > + div--; > + > + reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS); > + reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; > + } else { > + div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(priv->freq); > + reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS); > + reg |= SUN4I_CLK_CTL_CDR1(div); > + } > + > + writel(reg, SPI_REG(priv, SPI_CCR)); > + > if (priv->variant->has_soft_reset) > setbits_le32(SPI_REG(priv, SPI_GCR), > SPI_BIT(priv, SPI_GCR_SRST)); > > - setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) | > - SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW)); > + /* Setup the transfer control register */ > + reg = SPI_BIT(priv, SPI_TCR_CS_MANUAL) | > + SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW); > + > + if (priv->mode & SPI_CPOL) > + reg |= SPI_BIT(priv, SPI_TCR_CPOL); > + if (priv->mode & SPI_CPHA) > + reg |= SPI_BIT(priv, SPI_TCR_CPHA); > + > + writel(reg, SPI_REG(priv, SPI_TCR)); > > return 0; > } > @@ -329,67 +356,22 @@ static int sun4i_spi_set_speed(struct udevice *dev, uint speed) > { > struct sun4i_spi_plat *plat = dev_get_plat(dev); > struct sun4i_spi_priv *priv = dev_get_priv(dev); > - unsigned int div; > - u32 reg; > > if (speed > plat->max_hz) > speed = plat->max_hz; > > if (speed < SUN4I_SPI_MIN_RATE) > speed = SUN4I_SPI_MIN_RATE; > - /* > - * Setup clock divider. > - * > - * We have two choices there. Either we can use the clock > - * divide rate 1, which is calculated thanks to this formula: > - * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) > - * Or we can use CDR2, which is calculated with the formula: > - * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) > - * Whether we use the former or the latter is set through the > - * DRS bit. > - * > - * First try CDR2, and if we can't reach the expected > - * frequency, fall back to CDR1. > - */ > - > - div = SUN4I_SPI_MAX_RATE / (2 * speed); > - reg = readl(SPI_REG(priv, SPI_CCR)); > - > - if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { > - if (div > 0) > - div--; > - > - reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS); > - reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; > - } else { > - div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed); > - reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS); > - reg |= SUN4I_CLK_CTL_CDR1(div); > - } > > priv->freq = speed; > - writel(reg, SPI_REG(priv, SPI_CCR)); > - > return 0; > } > > static int sun4i_spi_set_mode(struct udevice *dev, uint mode) > { > struct sun4i_spi_priv *priv = dev_get_priv(dev); > - u32 reg; > - > - reg = readl(SPI_REG(priv, SPI_TCR)); > - reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA)); > - > - if (mode & SPI_CPOL) > - reg |= SPI_BIT(priv, SPI_TCR_CPOL); > - > - if (mode & SPI_CPHA) > - reg |= SPI_BIT(priv, SPI_TCR_CPHA); > > priv->mode = mode; > - writel(reg, SPI_REG(priv, SPI_TCR)); > - > return 0; > } > > @@ -441,7 +423,7 @@ static int sun4i_spi_of_to_plat(struct udevice *bus) > plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus); > plat->max_hz = fdtdec_get_int(gd->fdt_blob, node, > "spi-max-frequency", > - SUN4I_SPI_DEFAULT_RATE); > + SUN4I_SPI_MAX_RATE); > > if (plat->max_hz > SUN4I_SPI_MAX_RATE) > plat->max_hz = SUN4I_SPI_MAX_RATE;