From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECF6AC433EF for ; Tue, 28 Jun 2022 17:54:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DC5278407A; Tue, 28 Jun 2022 19:54:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="EnYNBicZ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2E06D842E3; Tue, 28 Jun 2022 19:54:52 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 160BF83EF2 for ; Tue, 28 Jun 2022 19:54:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id B9D3CB81C9E; Tue, 28 Jun 2022 17:54:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57E9EC3411D; Tue, 28 Jun 2022 17:54:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656438888; bh=rABMPIeaLrei4jLpSQWrXDmJJHhdrqhNjKcUAIpo0zg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EnYNBicZlHw/3JXm4pnTt9gAXLB7YPOmrX/suk/b2qUTvltXvnU2GnvpHJcgzv5ZL bwR4VP/LKVsMoezByEUq+Iz3FeTMy+Fu4H1WiHcN5fInVHh5oz7LIoahhKKfjg9fsO fB43rNKNwIyVXaYlIUvNUqFxkTfSN5awuowXArTwD4v6xhpVC0wm3X+FJ23BNsROO8 uhEEdPRgh9dcBPzLFnaewGPavwunBNx66XINL7uRH6DFWat015ixpxNK8P610hAte2 WSWUlwLZEEhiD3U21Ejh1lKE12QgejXzEAzhzJcLAaQaFyXuVJHnWCI52tFxEL8rT7 mSlPhXZMGeeHA== Received: by pali.im (Postfix) id 80A9E7AE; Tue, 28 Jun 2022 19:54:45 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , "Peng Fan (OSS)" , Tom Rini Cc: u-boot@lists.denx.de Subject: [PATCH v2] board: freescale: p1_p2_rdb_pc: Simplify SPL offset macros Date: Tue, 28 Jun 2022 19:53:55 +0200 Message-Id: <20220628175355.27817-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220405131237.405-9-pali@kernel.org> References: <20220405131237.405-9-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Now when CONFIG_SYS_TEXT_BASE has sane value, use it for calculation of other SPL offset values: CONFIG_SPL_MAX_SIZE, CONFIG_SYS_MMC_U_BOOT_* and CONFIG_SYS_SPI_FLASH_U_BOOT_* macros. No functional change. Signed-off-by: Pali Rohár --- Changes in v2: * Rebased on top of the U-Boot next branch, commit d61c11b8c894fad517677dc51ee82d1eade39c01 --- include/configs/p1_p2_rdb_pc.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 56a16502dcc7..7237e3c1a63c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -78,15 +78,15 @@ #ifdef CONFIG_SDCARD #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_MPC85XX_NO_RESETVEC #elif defined(CONFIG_SPIFLASH) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_MPC85XX_NO_RESETVEC #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -- 2.20.1