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[65.184.195.139]) by smtp.gmail.com with ESMTPSA id u16-20020a05620a0c5000b006a6ebde4799sm13245998qki.90.2022.06.28.12.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 12:08:58 -0700 (PDT) Date: Tue, 28 Jun 2022 15:08:57 -0400 From: Tom Rini To: Pali =?iso-8859-1?Q?Roh=E1r?= Cc: Priyanka Jain , "Peng Fan (OSS)" , u-boot@lists.denx.de Subject: Re: [PATCH v2] board: freescale: p1_p2_rdb_pc: Simplify SPL offset macros Message-ID: <20220628190857.GS1146598@bill-the-cat> References: <20220405131237.405-9-pali@kernel.org> <20220628175355.27817-1-pali@kernel.org> <20220628181742.GO1146598@bill-the-cat> <20220628182238.cmjhgpidicikyubo@pali> <20220628182852.GP1146598@bill-the-cat> <20220628183447.xnzwjxxnlabpf7on@pali> <20220628183911.GQ1146598@bill-the-cat> <20220628184144.5rygvzdznwgyb44j@pali> <20220628185326.GR1146598@bill-the-cat> <20220628185848.jelsy7xq2pn56cq7@pali> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="+d/sD+4Memv8CeGA" Content-Disposition: inline In-Reply-To: <20220628185848.jelsy7xq2pn56cq7@pali> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean --+d/sD+4Memv8CeGA Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Jun 28, 2022 at 08:58:48PM +0200, Pali Roh=E1r wrote: > On Tuesday 28 June 2022 14:53:26 Tom Rini wrote: > > On Tue, Jun 28, 2022 at 08:41:44PM +0200, Pali Roh=E1r wrote: > > > On Tuesday 28 June 2022 14:39:11 Tom Rini wrote: > > > > On Tue, Jun 28, 2022 at 08:34:47PM +0200, Pali Roh=E1r wrote: > > > > > On Tuesday 28 June 2022 14:28:52 Tom Rini wrote: > > > > > > On Tue, Jun 28, 2022 at 08:22:38PM +0200, Pali Roh=E1r wrote: > > > > > > > On Tuesday 28 June 2022 14:17:42 Tom Rini wrote: > > > > > > > > On Tue, Jun 28, 2022 at 07:53:55PM +0200, Pali Roh=E1r wrot= e: > > > > > > > >=20 > > > > > > > > > Now when CONFIG_SYS_TEXT_BASE has sane value, use it for = calculation of > > > > > > > > > other SPL offset values: CONFIG_SPL_MAX_SIZE, CONFIG_SYS_= MMC_U_BOOT_* and > > > > > > > > > CONFIG_SYS_SPI_FLASH_U_BOOT_* macros. > > > > > > > > >=20 > > > > > > > > > No functional change. > > > > > > > > >=20 > > > > > > > > > Signed-off-by: Pali Roh=E1r > > > > > > > > > --- > > > > > > > > > Changes in v2: > > > > > > > > > * Rebased on top of the U-Boot next branch, commit d61c11= b8c894fad517677dc51ee82d1eade39c01 > > > > > > > > > --- > > > > > > > > > include/configs/p1_p2_rdb_pc.h | 12 ++++++------ > > > > > > > > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > > > > > >=20 > > > > > > > > > diff --git a/include/configs/p1_p2_rdb_pc.h b/include/con= figs/p1_p2_rdb_pc.h > > > > > > > > > index 56a16502dcc7..7237e3c1a63c 100644 > > > > > > > > > --- a/include/configs/p1_p2_rdb_pc.h > > > > > > > > > +++ b/include/configs/p1_p2_rdb_pc.h > > > > > > > > > @@ -78,15 +78,15 @@ > > > > > > > > > =20 > > > > > > > > > #ifdef CONFIG_SDCARD > > > > > > > > > #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) > > > > > > > > > -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) > > > > > > > > > -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) > > > > > > > > > -#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) > > > > > > > > > +#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE > > > > > > > > > +#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE > > > > > > > > > +#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO > > > > > > > > > #define CONFIG_SYS_MPC85XX_NO_RESETVEC > > > > > > > > > #elif defined(CONFIG_SPIFLASH) > > > > > > > > > #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) > > > > > > > > > -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) > > > > > > > > > -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) > > > > > > > > > -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) > > > > > > > > > +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_TEXT= _BASE > > > > > > > > > +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_SYS_TEX= T_BASE > > > > > > > > > +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_= TO > > > > > > > > > #define CONFIG_SYS_MPC85XX_NO_RESETVEC > > > > > > > > > #elif defined(CONFIG_MTD_RAW_NAND) > > > > > > > > > #ifdef CONFIG_TPL_BUILD > > > > > > > >=20 > > > > > > > > So, this is entirely a PowerPC spl set of CONFIG variables.= Can we move > > > > > > > > them to Kconfig, and use default xxx as you're changing the= m to above? > > > > > > > > The other platforms using this look to be doing the same at= first > > > > > > > > glance. > > > > > > > >=20 > > > > > > > > --=20 > > > > > > > > Tom > > > > > > >=20 > > > > > > > Not sure how to do it right now. CONFIG_SYS_MMC_U_BOOT_OFFS w= ould need > > > > > > > to be adjusted by size of boot sector, as is in this patch: > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/202204051340= 32.704-3-pali@kernel.org/ > > > > > > >=20 > > > > > > > So I just sent patch in current form which simplify definitio= ns of > > > > > > > CONFIG_SYS_MMC_U_BOOT_* and CONFIG_SYS_SPI_FLASH_U_BOOT_* mac= ros. > > > > > >=20 > > > > > > Given the limited places we use CONFIG_SYS_MMC_U_BOOT_OFFS (two= spots, > > > > > > one file), remove it from CONFIG space, make it file local, and > > > > > > FSL_PREPBL_ESDHC_BOOT_SECTOR will be in Kconfig to start with? = I'm > > > > > > taking a harder look at what CONFIG_SYS_* can be moved to Kconf= ig, and > > > > > > what needs to be just something else, and what can be cleaned u= p / > > > > > > removed, so I really want to figure out a solution here that mi= grates > > > > > > the symbols or removes them from CONFIG namespace. > > > > > >=20 > > > > > > --=20 > > > > > > Tom > > > > >=20 > > > > > More than month ago I proposed different solution, prepare codeba= se to > > > > > completely drop CONFIG_SYS_MMC_U_BOOT_OFFS option. But nobody rea= cted to > > > > > it and now I see on patchwork just "Changes Requested". > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220511183332.1= 362-2-pali@kernel.org/ > > > >=20 > > > > Er, I see > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220511183332.136= 2-1-pali@kernel.org/ > > > > notes it fails to build, so that's probably the changes requested. > > > >=20 > > > > --=20 > > > > Tom > > >=20 > > > V2 for that build failure already exists and half hour ago I sent > > > another reminder for v2: > > > https://lore.kernel.org/u-boot/20220628181436.iwmwvvoithgwp6pu@pali/ > > > but it has nothing with CONFIG_SYS_MMC_U_BOOT_OFFS... > >=20 > > Patch 1/3 in the series causes fails to build errors, the whole series > > gets changes requested, that's normal to me and expecting the whole > > series to be reposted. >=20 > See the previous link. I have already rebased and resent first patch as v= 2. Yes, that's my point. You should have resent the whole series, not just that first patch. Why? Well, this feels like we're getting back to the state much of the N900 patches got to where it was really hard for Lokesh, or myself, to figure out the correct order to apply N patches in, with some of them having been reposted / rebased and others depending on those patches. The v2 you link above isn't "v2 1/3", but just "v2". So, reposting the whole series is preferred. --=20 Tom --+d/sD+4Memv8CeGA Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmK7UcUACgkQFHw5/5Y0 tywBhgv+Ixbh3XEoPtmlqW7U7lfUBlEyBOHUAePAcdRsMaoaIPHW7orJ2IjPu9QJ vhUdUUMTeCX44OuH8bbD0vyeaxqpT4cFmx4OJ89ebFo6Rx3fRDOgfQqzPmbNj05N t8ShJiV5F6Kl7lh52XEDBQpKK5esiUkiV4UprDFJhOGhhn3oX+WIryMwwM5rsYHs GVHpwfIAlX1AODJt1uRYq8xOiiaI3+Ym0TuHHciNSr3QSaGcR7//+KViFhexE88U yW6IeKxG3Gr26S0NbmVAlyT1OijTkN6fbD2uykOjwhRDjMJsn7eJpKR6AUNzPKuK grvGvGWsmNFDQTtsZqGqRZWwyOdLAfK23lLbYNqZpjLL/8SL70qbQheWZW4RZ2Rt VIJINiDUqPsjLoYgpNmIEnWpbV9Ofh1DfMJ2UMQDcKv5c6xjD4OGRuQ0QnewWBJW qktWNd92kgtPAnGCXzkjXTpJNnKcVwHIiIfmoEfhoIu+wYLT/tqhI8wWL2R7YvTe tyvx2xhB =6ldl -----END PGP SIGNATURE----- --+d/sD+4Memv8CeGA--