Re: [PATCH 1/3] board: freescale: p1_p2_rdb_pc: Add workaround for board reset reboot loop

["Pali Rohár" <pali@kernel.org>]

Hello! This change is waiting here since May 01.

On Tuesday 05 July 2022 18:39:19 Pali Rohár wrote:
> PING?
> 
> On Sunday 01 May 2022 14:23:12 Pali Rohár wrote:
> > CPLD's system reset register on P1/P2 RDB boards is not autocleared after
> > flipping it. If this register is set to one then CPLD triggers reset of CPU
> > in few ms.
> > 
> > This means that trying to reset board via CPLD system reset register cause
> > reboot loop. To prevent this reboot loop, the only workaround is to try to
> > clear CPLD's system reset register as early as possible. U-Boot is already
> > doing it in its board_early_init_f() function, which seems to be enough as
> > register is cleared prior CPLD triggers another reset.
> > 
> > But board_early_init_f() is not called from SPL and therefore usage of SPL
> > can cause reboot loop.
> > 
> > To prevent reboot loop when using SPL, calls board_early_init_f() function
> > in SPL too. For accessing CPLD memory space it is needed to have CPLD entry
> > in TLB.
> > 
> > With this change it is possible to trigger board reset via CPLD's system
> > reset register on P2020 RDB board.
> > 
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > ---
> >  board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 10 ++++++++++
> >  board/freescale/p1_p2_rdb_pc/spl.c          |  6 ++++++
> >  board/freescale/p1_p2_rdb_pc/tlb.c          |  2 +-
> >  3 files changed, 17 insertions(+), 1 deletion(-)
> > 
> > diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > index 7b168fa091b1..26ea8a525228 100644
> > --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > @@ -91,6 +91,16 @@ void board_cpld_init(void)
> >  	out_8(&cpld_data->status_led, CPLD_STATUS_LED);
> >  	out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
> >  	out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
> > +
> > +	/*
> > +	 * CPLD's system reset register on P1/P2 RDB boards is not autocleared
> > +	 * after flipping it. If this register is set to one then CPLD triggers
> > +	 * reset of CPU in few ms.
> > +	 *
> > +	 * This means that trying to reset board via CPLD system reset register
> > +	 * cause reboot loop. To prevent this reboot loop, the only workaround
> > +	 * is to try to clear CPLD's system reset register as early as possible.
> > +	 */
> >  	out_8(&cpld_data->system_rst, CPLD_SYS_RST);
> >  }
> >  
> > diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
> > index 22156f2824ec..def28665960d 100644
> > --- a/board/freescale/p1_p2_rdb_pc/spl.c
> > +++ b/board/freescale/p1_p2_rdb_pc/spl.c
> > @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag)
> >  	u32 plat_ratio, bus_clk;
> >  	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
> >  
> > +	/*
> > +	 * Call board_early_init_f() as early as possible as it workarounds
> > +	 * reboot loop due to broken CPLD state machine for reset line.
> > +	 */
> > +	board_early_init_f();
> > +
> >  	console_init_f();
> >  
> >  	/* Set pmuxcr to allow both i2c1 and i2c2 */
> > diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
> > index 13f3a1edf68d..2d431d6d0d90 100644
> > --- a/board/freescale/p1_p2_rdb_pc/tlb.c
> > +++ b/board/freescale/p1_p2_rdb_pc/tlb.c
> > @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
> >  			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> >  			0, 5, BOOKE_PAGESZ_1M, 1),
> >  #endif
> > +#endif /* not SPL */
> >  
> >  	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
> >  			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> >  			0, 6, BOOKE_PAGESZ_1M, 1),
> > -#endif /* not SPL */
> >  
> >  #ifdef CONFIG_SYS_NAND_BASE
> >  	/* *I*G - NAND */
> > -- 
> > 2.20.1
> >