From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBA26C433EF for ; Tue, 12 Jul 2022 13:51:08 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 37BAB84147; Tue, 12 Jul 2022 15:51:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="oBdjV7rs"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0010E84158; Tue, 12 Jul 2022 15:51:02 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0EA4E8411C for ; Tue, 12 Jul 2022 15:51:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6A431617BE; Tue, 12 Jul 2022 13:50:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 802CAC3411C; Tue, 12 Jul 2022 13:50:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657633857; bh=Tf+uEvPARl6ZNpmeYbJlCgYD6BxWgVVqqkY9KEhsXY0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=oBdjV7rsaHCHJD0z3FNzU34YPV+dTwk+2KcplF77upDnIQHlKEFiKLsU8veWuYuMq cosJ+oPOkyY9Ec/ULcZriyotT9FOWWmK/vAlLfrlt+8Ip/5TjmmeozhsPKkN7951yU dt6qGZmuPUGAMd7OFzF8aG/YzkCNfwhvxIntHmAiRBmKda5BH5J9nJQ8sw2iHTBzI6 gYECtu8OB4ZDveVF4udfHg3AM3RfkF1oqBlqlrJp5eERV31adJZi+/smeyUeWHgIHV kGv/ELv4GgAbF20Dsdl+FO6Thc5btvhHlude4sDkcPQa9r9B8NrsuYfDIFXDa9xojn SiOTEuJxV8fGw== Received: by pali.im (Postfix) id 4CDE5B2D; Tue, 12 Jul 2022 15:50:54 +0200 (CEST) Date: Tue, 12 Jul 2022 15:50:54 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: "Peng Fan (OSS)" , Priyanka Jain , Sinan Akman , Tom Rini Cc: u-boot@lists.denx.de Subject: Re: [PATCH 1/3] board: freescale: p1_p2_rdb_pc: Add workaround for board reset reboot loop Message-ID: <20220712135054.7gemo7x5mig3ioxm@pali> References: <20220501122314.32626-1-pali@kernel.org> <20220705163919.rozmupridbjuzw6h@pali> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220705163919.rozmupridbjuzw6h@pali> User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hello! This change is waiting here since May 01. On Tuesday 05 July 2022 18:39:19 Pali Rohár wrote: > PING? > > On Sunday 01 May 2022 14:23:12 Pali Rohár wrote: > > CPLD's system reset register on P1/P2 RDB boards is not autocleared after > > flipping it. If this register is set to one then CPLD triggers reset of CPU > > in few ms. > > > > This means that trying to reset board via CPLD system reset register cause > > reboot loop. To prevent this reboot loop, the only workaround is to try to > > clear CPLD's system reset register as early as possible. U-Boot is already > > doing it in its board_early_init_f() function, which seems to be enough as > > register is cleared prior CPLD triggers another reset. > > > > But board_early_init_f() is not called from SPL and therefore usage of SPL > > can cause reboot loop. > > > > To prevent reboot loop when using SPL, calls board_early_init_f() function > > in SPL too. For accessing CPLD memory space it is needed to have CPLD entry > > in TLB. > > > > With this change it is possible to trigger board reset via CPLD's system > > reset register on P2020 RDB board. > > > > Signed-off-by: Pali Rohár > > --- > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 10 ++++++++++ > > board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ > > board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- > > 3 files changed, 17 insertions(+), 1 deletion(-) > > > > diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c > > index 7b168fa091b1..26ea8a525228 100644 > > --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c > > +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c > > @@ -91,6 +91,16 @@ void board_cpld_init(void) > > out_8(&cpld_data->status_led, CPLD_STATUS_LED); > > out_8(&cpld_data->fxo_led, CPLD_FXO_LED); > > out_8(&cpld_data->fxs_led, CPLD_FXS_LED); > > + > > + /* > > + * CPLD's system reset register on P1/P2 RDB boards is not autocleared > > + * after flipping it. If this register is set to one then CPLD triggers > > + * reset of CPU in few ms. > > + * > > + * This means that trying to reset board via CPLD system reset register > > + * cause reboot loop. To prevent this reboot loop, the only workaround > > + * is to try to clear CPLD's system reset register as early as possible. > > + */ > > out_8(&cpld_data->system_rst, CPLD_SYS_RST); > > } > > > > diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c > > index 22156f2824ec..def28665960d 100644 > > --- a/board/freescale/p1_p2_rdb_pc/spl.c > > +++ b/board/freescale/p1_p2_rdb_pc/spl.c > > @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) > > u32 plat_ratio, bus_clk; > > ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; > > > > + /* > > + * Call board_early_init_f() as early as possible as it workarounds > > + * reboot loop due to broken CPLD state machine for reset line. > > + */ > > + board_early_init_f(); > > + > > console_init_f(); > > > > /* Set pmuxcr to allow both i2c1 and i2c2 */ > > diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c > > index 13f3a1edf68d..2d431d6d0d90 100644 > > --- a/board/freescale/p1_p2_rdb_pc/tlb.c > > +++ b/board/freescale/p1_p2_rdb_pc/tlb.c > > @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { > > MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > 0, 5, BOOKE_PAGESZ_1M, 1), > > #endif > > +#endif /* not SPL */ > > > > SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, > > MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > 0, 6, BOOKE_PAGESZ_1M, 1), > > -#endif /* not SPL */ > > > > #ifdef CONFIG_SYS_NAND_BASE > > /* *I*G - NAND */ > > -- > > 2.20.1 > >