[PATCH 08/14] imx: kontron-sl-mx8mm: Use new LPDDR4 config parameters

Frieder Schrempf
2022-07-13T09:54:22Z

These parameters are needed for stable performance on new hardware
with Nanya LPDDR4 chips.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
board/kontron/sl-mx8mm/lpddr4_timing.c | 184 +++++++------------------
board/kontron/sl-mx8mm/spl.c | 8 +-
2 files changed, 55 insertions(+), 137 deletions(-)

diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c b/board/kontron/sl-mx8mm/lpddr4_timing.c
index cdde6ac0dc0..74b79c7a009 100644
--- a/board/kontron/sl-mx8mm/lpddr4_timing.c
+++ b/board/kontron/sl-mx8mm/lpddr4_timing.c
@@ -15,13 +15,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x223 },
{ 0x3d400024, 0x3a980 },
- { 0x3d400064, 0x5b0087 },
+ { 0x3d400064, 0x5b00d2 },
{ 0x3d4000d0, 0xc00305ba },
{ 0x3d4000d4, 0x940000 },
{ 0x3d4000dc, 0xd4002d },
{ 0x3d4000e0, 0x310000 },
- { 0x3d4000e8, 0x66004d },
- { 0x3d4000ec, 0x16004d },
+ { 0x3d4000e8, 0x63004d },
+ { 0x3d4000ec, 0x15004d },
{ 0x3d400100, 0x191e1920 },
{ 0x3d400104, 0x60630 },
{ 0x3d40010c, 0xb0b000 },
@@ -88,30 +88,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d403020, 0x21 },
- { 0x3d403024, 0x1f40 },
- { 0x3d403050, 0x20d040 },
- { 0x3d403064, 0x30007 },
- { 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x310000 },
- { 0x3d4030e8, 0x66004d },
- { 0x3d4030ec, 0x16004d },
- { 0x3d403100, 0xa010102 },
- { 0x3d403104, 0x30404 },
- { 0x3d403108, 0x203060b },
- { 0x3d40310c, 0x505000 },
- { 0x3d403110, 0x2040202 },
- { 0x3d403114, 0x2030202 },
- { 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
- { 0x3d403130, 0x20300 },
- { 0x3d403134, 0xa100002 },
- { 0x3d403138, 0x8 },
- { 0x3d403144, 0x50003 },
- { 0x3d403180, 0x190004 },
- { 0x3d403190, 0x3818200 },
- { 0x3d403194, 0x80303 },
- { 0x3d4031b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
{ 0x3d400028, 0x0 },
};

@@ -165,14 +142,6 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x11215f, 0x1ff },
{ 0x11305f, 0x1ff },
{ 0x11315f, 0x1ff },
- { 0x21005f, 0x1ff },
- { 0x21015f, 0x1ff },
- { 0x21105f, 0x1ff },
- { 0x21115f, 0x1ff },
- { 0x21205f, 0x1ff },
- { 0x21215f, 0x1ff },
- { 0x21305f, 0x1ff },
- { 0x21315f, 0x1ff },
{ 0x55, 0x1ff },
{ 0x1055, 0x1ff },
{ 0x2055, 0x1ff },
@@ -185,22 +154,16 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x9055, 0x1ff },
{ 0x200c5, 0x19 },
{ 0x1200c5, 0x7 },
- { 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
{ 0x12002e, 0x2 },
- { 0x22002e, 0x2 },
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
- { 0x290204, 0x0 },
{ 0x20024, 0x1ab },
{ 0x2003a, 0x0 },
{ 0x120024, 0x1ab },
{ 0x2003a, 0x0 },
- { 0x220024, 0x1ab },
- { 0x2003a, 0x0 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
- { 0x220056, 0x3 },
{ 0x1004d, 0xe00 },
{ 0x1014d, 0xe00 },
{ 0x1104d, 0xe00 },
@@ -217,54 +180,37 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x11214d, 0xe00 },
{ 0x11304d, 0xe00 },
{ 0x11314d, 0xe00 },
- { 0x21004d, 0xe00 },
- { 0x21014d, 0xe00 },
- { 0x21104d, 0xe00 },
- { 0x21114d, 0xe00 },
- { 0x21204d, 0xe00 },
- { 0x21214d, 0xe00 },
- { 0x21304d, 0xe00 },
- { 0x21314d, 0xe00 },
- { 0x10049, 0xeba },
- { 0x10149, 0xeba },
- { 0x11049, 0xeba },
- { 0x11149, 0xeba },
- { 0x12049, 0xeba },
- { 0x12149, 0xeba },
- { 0x13049, 0xeba },
- { 0x13149, 0xeba },
- { 0x110049, 0xeba },
- { 0x110149, 0xeba },
- { 0x111049, 0xeba },
- { 0x111149, 0xeba },
- { 0x112049, 0xeba },
- { 0x112149, 0xeba },
- { 0x113049, 0xeba },
- { 0x113149, 0xeba },
- { 0x210049, 0xeba },
- { 0x210149, 0xeba },
- { 0x211049, 0xeba },
- { 0x211149, 0xeba },
- { 0x212049, 0xeba },
- { 0x212149, 0xeba },
- { 0x213049, 0xeba },
- { 0x213149, 0xeba },
- { 0x43, 0x63 },
- { 0x1043, 0x63 },
- { 0x2043, 0x63 },
- { 0x3043, 0x63 },
- { 0x4043, 0x63 },
- { 0x5043, 0x63 },
- { 0x6043, 0x63 },
- { 0x7043, 0x63 },
- { 0x8043, 0x63 },
- { 0x9043, 0x63 },
+ { 0x10049, 0x69a },
+ { 0x10149, 0x69a },
+ { 0x11049, 0x69a },
+ { 0x11149, 0x69a },
+ { 0x12049, 0x69a },
+ { 0x12149, 0x69a },
+ { 0x13049, 0x69a },
+ { 0x13149, 0x69a },
+ { 0x110049, 0x69a },
+ { 0x110149, 0x69a },
+ { 0x111049, 0x69a },
+ { 0x111149, 0x69a },
+ { 0x112049, 0x69a },
+ { 0x112149, 0x69a },
+ { 0x113049, 0x69a },
+ { 0x113149, 0x69a },
+ { 0x43, 0xe7 },
+ { 0x1043, 0xe7 },
+ { 0x2043, 0xe7 },
+ { 0x3043, 0xe7 },
+ { 0x4043, 0xe7 },
+ { 0x5043, 0xe7 },
+ { 0x6043, 0xe7 },
+ { 0x7043, 0xe7 },
+ { 0x8043, 0xe7 },
+ { 0x9043, 0xe7 },
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
{ 0x20008, 0x2ee },
{ 0x120008, 0x64 },
- { 0x220008, 0x19 },
{ 0x20088, 0x9 },
{ 0x200b2, 0xdc },
{ 0x10043, 0x5a1 },
@@ -284,39 +230,25 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x112143, 0x5a1 },
{ 0x113043, 0x5a1 },
{ 0x113143, 0x5a1 },
- { 0x2200b2, 0xdc },
- { 0x210043, 0x5a1 },
- { 0x210143, 0x5a1 },
- { 0x211043, 0x5a1 },
- { 0x211143, 0x5a1 },
- { 0x212043, 0x5a1 },
- { 0x212143, 0x5a1 },
- { 0x213043, 0x5a1 },
- { 0x213143, 0x5a1 },
{ 0x200fa, 0x1 },
{ 0x1200fa, 0x1 },
- { 0x2200fa, 0x1 },
{ 0x20019, 0x1 },
{ 0x120019, 0x1 },
- { 0x220019, 0x1 },
- { 0x200f0, 0x660 },
+ { 0x200f0, 0x60 },
{ 0x200f1, 0x0 },
{ 0x200f2, 0x4444 },
{ 0x200f3, 0x8888 },
- { 0x200f4, 0x5665 },
+ { 0x200f4, 0x5565 },
{ 0x200f5, 0x0 },
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
{ 0x2002d, 0x0 },
{ 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
{ 0x200c7, 0x21 },
{ 0x1200c7, 0x21 },
- { 0x2200c7, 0x21 },
{ 0x200ca, 0x24 },
{ 0x1200ca, 0x24 },
- { 0x2200ca, 0x24 },
};

/* ddr phy trained csr */
@@ -1047,37 +979,36 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
- { 0x54005, 0x2228 },
+ { 0x54005, 0x3028 },
{ 0x54006, 0x11 },
{ 0x54008, 0x131f },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
- { 0x5400d, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
+ { 0x5401b, 0x4d63 },
{ 0x5401c, 0x4d00 },
- { 0x5401e, 0x16 },
+ { 0x5401e, 0x15 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
+ { 0x54021, 0x4d63 },
{ 0x54022, 0x4d00 },
- { 0x54024, 0x16 },
+ { 0x54024, 0x15 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
- { 0x54034, 0x6600 },
+ { 0x54034, 0x6300 },
{ 0x54035, 0x4d },
{ 0x54036, 0x4d },
- { 0x54037, 0x1600 },
+ { 0x54037, 0x1500 },
{ 0x54038, 0xd400 },
{ 0x54039, 0x312d },
- { 0x5403a, 0x6600 },
+ { 0x5403a, 0x6300 },
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
+ { 0x5403d, 0x1500 },
{ 0xd0000, 0x1 },
};

@@ -1087,12 +1018,11 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0x54002, 0x101 },
{ 0x54003, 0x190 },
{ 0x54004, 0x2 },
- { 0x54005, 0x2228 },
+ { 0x54005, 0x3028 },
{ 0x54006, 0x11 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
- { 0x5400d, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x31 },
@@ -1126,7 +1056,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
- { 0x54005, 0x2228 },
+ { 0x54005, 0x3028 },
{ 0x54006, 0x11 },
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
@@ -1136,28 +1066,28 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0x54012, 0x310 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
+ { 0x5401b, 0x4d63 },
{ 0x5401c, 0x4d00 },
- { 0x5401e, 0x16 },
+ { 0x5401e, 0x15 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
+ { 0x54021, 0x4d63 },
{ 0x54022, 0x4d00 },
- { 0x54024, 0x16 },
+ { 0x54024, 0x15 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
- { 0x54034, 0x6600 },
+ { 0x54034, 0x6300 },
{ 0x54035, 0x4d },
{ 0x54036, 0x4d },
- { 0x54037, 0x1600 },
+ { 0x54037, 0x1500 },
{ 0x54038, 0xd400 },
{ 0x54039, 0x312d },
- { 0x5403a, 0x6600 },
+ { 0x5403a, 0x6300 },
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
+ { 0x5403d, 0x1500 },
{ 0xd0000, 0x1 },
};

@@ -1659,10 +1589,6 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x12000c, 0x19 },
{ 0x12000d, 0xfa },
{ 0x12000e, 0x10 },
- { 0x22000b, 0x3 },
- { 0x22000c, 0x6 },
- { 0x22000d, 0x3e },
- { 0x22000e, 0x10 },
{ 0x9000c, 0x0 },
{ 0x9000d, 0x173 },
{ 0x9000e, 0x60 },
@@ -1675,8 +1601,6 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x20011, 0x3 },
{ 0x120010, 0x5a },
{ 0x120011, 0x3 },
- { 0x220010, 0x5a },
- { 0x220011, 0x3 },
{ 0x40080, 0xe0 },
{ 0x40081, 0x12 },
{ 0x40082, 0xe0 },
@@ -1689,12 +1613,6 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x140083, 0x12 },
{ 0x140084, 0xe0 },
{ 0x140085, 0x12 },
- { 0x240080, 0xe0 },
- { 0x240081, 0x12 },
- { 0x240082, 0xe0 },
- { 0x240083, 0x12 },
- { 0x240084, 0xe0 },
- { 0x240085, 0x12 },
{ 0x400fd, 0xf },
{ 0x10011, 0x1 },
{ 0x10012, 0x1 },
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index 8464e782e49..212d712de6f 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -89,10 +89,10 @@ static void spl_dram_init(void)
dram_timing.ddrc_cfg[2].val = 0xa1080020;
dram_timing.ddrc_cfg[37].val = 0x1f;

- dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110;
- dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1;
- dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110;
- dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
+ dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x110;
+ dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x1;
+ dram_timing.fsp_msg[1].fsp_cfg[9].val = 0x110;
+ dram_timing.fsp_msg[1].fsp_cfg[21].val = 0x1;
dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;

--
2.37.0