From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA666CCA479 for ; Wed, 13 Jul 2022 09:54:10 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8B09184417; Wed, 13 Jul 2022 11:53:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=fris.de header.i=@fris.de header.b="tl2DVtKs"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9778184233; Wed, 13 Jul 2022 11:53:20 +0200 (CEST) Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6136284312 for ; Wed, 13 Jul 2022 11:53:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=frieder@fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9B51CBFABB; Wed, 13 Jul 2022 11:53:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1657705984; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=uMq2IJC8xduu3Wdff77m6OUj0ipVfx6JZgtKs6JqTlc=; b=tl2DVtKsSGk96cw7W8bX7RKH/Gdooake4L9WpW41X8OP+aPB1+1Ved8sITkRqQNLcPdLKh AB2IGKyDgUhZWQCRfCnDOg4fokK+xeZWCUfNsWwcaYM9hcbjZmhjpu0AjJlq2ZMdo2ra9b XIbfq4G0evWa2lt8Jo+Etug5MuTCBQen6BwRgqTx2vkLpDp9Tqd5npky3DEqzOesDomEKS Kcx4eVfga9byr6sgA17eAIovE/OWBkXu559DFO5GzvdqERzHV6jwMuwt8AV9CZgVka/6OF k3/X3ODIBVpqNnFBmOv2cHGD2qiiYEd/b9Vo/TyQzkudxsAgsvuaCE6PLFmejA== From: Frieder Schrempf To: Fabio Estevam , Frieder Schrempf , Stefano Babic , u-boot@lists.denx.de Cc: Fabio Estevam , "NXP i.MX U-Boot Team" , Peng Fan Subject: [PATCH 07/14] imx: kontron-sl-mx8mm: Remove 100mt DDR setpoint Date: Wed, 13 Jul 2022 11:52:18 +0200 Message-Id: <20220713095229.43274-8-frieder@fris.de> In-Reply-To: <20220713095229.43274-1-frieder@fris.de> References: <20220713095229.43274-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Frieder Schrempf The new stable configuration is missing the 100mt setpoint, remove it before updating the config to make sure the changes are separated cleanly. Signed-off-by: Frieder Schrempf --- arch/arm/dts/imx8mm-kontron-n801x-som.dtsi | 4 -- board/kontron/sl-mx8mm/lpddr4_timing.c | 49 +--------------------- board/kontron/sl-mx8mm/spl.c | 2 - 3 files changed, 1 insertion(+), 54 deletions(-) diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi index 8f90eb02550..7e80008da29 100644 --- a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi @@ -46,10 +46,6 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - opp-100M { opp-hz = /bits/ 64 <100000000>; }; diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c b/board/kontron/sl-mx8mm/lpddr4_timing.c index a8dcaafb180..cdde6ac0dc0 100644 --- a/board/kontron/sl-mx8mm/lpddr4_timing.c +++ b/board/kontron/sl-mx8mm/lpddr4_timing.c @@ -1121,46 +1121,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0xd0000, 0x1 }, }; -/* P2 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - /* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, @@ -1812,13 +1772,6 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg = ddr_fsp1_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, { /* P0 3000mts 2D */ .drate = 3000, @@ -1840,5 +1793,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 3000, 400, }, }; diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index c379d37f1e8..8464e782e49 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -95,8 +95,6 @@ static void spl_dram_init(void) dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1; dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110; dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1; - dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110; - dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1; if (!ddr_init(&dram_timing)) { if (check_ram_available(SZ_2G)) -- 2.37.0